Performance optimization of pipelined circuits

1990 IEEE International Conference on Computer-Aided Design. Digest of Technical Papers

Volumn , Issue , 1990, Pages 410-413

  Malik, Sharad ^a   Singh, Kanwar Jit ^a   Brayton, R K ^a   Sangiovanni Vincentelli, Alberto ^a  

^a UNIVERSITY OF CALIFORNIA   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTER ARCHITECTURE;

LATCHES; PIPELINED CIRCUITS;

LOGIC CIRCUITS, COMBINATORIAL;

EID: 0025531688     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (10)