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Volumn 39, Issue 1-4, 1997, Pages 123-137

Low power / low voltage CMOS technologies, A comparative analysis

Author keywords

[No Author keywords available]

Indexed keywords

CMOS INTEGRATED CIRCUITS; ELECTRONICS ENGINEERING; PERFORMANCE; TECHNOLOGY;

EID: 0031371811     PISSN: 01679317     EISSN: None     Source Type: Journal    
DOI: 10.1016/S0167-9317(97)00170-6     Document Type: Article
Times cited : (4)

References (48)
  • 1
    • 0029292870 scopus 로고
    • Technology leverage for ultra-low power information systems
    • Apr.
    • J. M. C. Stork, "Technology Leverage for ultra-low power information systems," Proceedings of the IEEE, vol. 83, No. 4, pp. 607-618, Apr. 1995
    • (1995) Proceedings of the IEEE , vol.83 , Issue.4 , pp. 607-618
    • Stork, J.M.C.1
  • 2
    • 0029292398 scopus 로고
    • Low power microelectronics: Retrospect and prospect
    • Apr.
    • J. D. Meindl, "Low power microelectronics: retrospect and prospect," Proceedings of the IEEE, vol. 83, No.4, pp. 619-635, Apr. 1995
    • (1995) Proceedings of the IEEE , vol.83 , Issue.4 , pp. 619-635
    • Meindl, J.D.1
  • 3
    • 0029292445 scopus 로고
    • CMOS scaling for high performance and low power - The next ten years
    • Apr.
    • B. Davari, R. H. Dennard, and G. G. Shahidi, "CMOS scaling for high performance and low power - the next ten years," Proceedings of the IEEE, vol. 83, No.4, pp. 595-606, Apr. 1995
    • (1995) Proceedings of the IEEE , vol.83 , Issue.4 , pp. 595-606
    • Davari, B.1    Dennard, R.H.2    Shahidi, G.G.3
  • 4
    • 0027649412 scopus 로고
    • Trends and limits in monolithic integration by increasing the die area
    • Aug.
    • C. A. Warwick and A. Ourmazd, "Trends and limits in monolithic integration by increasing the die area," IEEE Trans. Semicond. Manuf., vol. 6, pp. 284-289, Aug. 1993
    • (1993) IEEE Trans. Semicond. Manuf. , vol.6 , pp. 284-289
    • Warwick, C.A.1    Ourmazd, A.2
  • 8
    • 0000901940 scopus 로고
    • Fundamental limitations in microelectronics -I. MOS technology
    • B. Hoeneisen and C. A. Mead, " Fundamental limitations in microelectronics -I. MOS technology," Solid State Electron., vol. 15, pp. 819-829, 1972.
    • (1972) Solid State Electron. , vol.15 , pp. 819-829
    • Hoeneisen, B.1    Mead, C.A.2
  • 9
    • 0021406605 scopus 로고
    • Gen-eralized scaling theory and its application to a 1/4 micron MOSFET design
    • Apr.
    • G. Baccarani, M. R. Wordeman, and R. H. Dennard, "Gen-eralized scaling theory and its application to a 1/4 micron MOSFET design," IEEE Trans. Electron Devices, vol. ED-31, pp. 425-462, Apr. 1984.
    • (1984) IEEE Trans. Electron Devices , vol.ED-31 , pp. 425-462
    • Baccarani, G.1    Wordeman, M.R.2    Dennard, R.H.3
  • 10
    • 0020194040 scopus 로고
    • Short channel MOSFET threshold model
    • Oct.
    • K. N. Ratnakumer and J. Meindl, "Short channel MOSFET threshold model," IEEE J. Solid-State Circ., vol. SC-17, pp. 937-947, Oct. 1982.
    • (1982) IEEE J. Solid-state Circ. , vol.SC-17 , pp. 937-947
    • Ratnakumer, K.N.1    Meindl, J.2
  • 11
    • 0016113965 scopus 로고
    • A simple theory to predict the threshold voltage of short channel IGFET's
    • L. D. Yau, "A simple theory to predict the threshold voltage of short channel IGFET's," Solid-State Electron., vol. 17, pp. 1059-1063, 1974.
    • (1974) Solid-state Electron. , vol.17 , pp. 1059-1063
    • Yau, L.D.1
  • 12
    • 0018455052 scopus 로고
    • VLSI limitations from drain induced barrier lowering
    • R. R. Troutman, "VLSI limitations from drain induced barrier lowering," IEEE Trans. Electron Devices, vol. ED-26, pp. 461-469, 1979.
    • (1979) IEEE Trans. Electron Devices , vol.ED-26 , pp. 461-469
    • Troutman, R.R.1
  • 13
    • 84907697821 scopus 로고
    • Opportunities for scaling MOSFET's for GSI
    • B. Agrawal, V. K. De, and J. D. Meindl, "Opportunities for scaling MOSFET's for GSI," Proc. ESSDERC 1993, pp. 919-926.
    • (1993) Proc. ESSDERC , pp. 919-926
    • Agrawal, B.1    De, V.K.2    Meindl, J.D.3
  • 14
    • 84963965381 scopus 로고    scopus 로고
    • A new scaling method for 0.1-0.25 micron MOSFET
    • C. Fiegna et al., "A new scaling method for 0.1-0.25 micron MOSFET," May 1993 Symp. VLSI Tech. Dig., pp.33-34.
    • May 1993 Symp. VLSI Tech. Dig. , pp. 33-34
    • Fiegna, C.1
  • 15
    • 0028459988 scopus 로고
    • MOSFET scaling in the next decade and beyond
    • Jun.
    • C. Hu, "MOSFET scaling in the next decade and beyond," Semicon Int., pp. 105-114, Jun. 1994.
    • (1994) Semicon Int. , pp. 105-114
    • Hu, C.1
  • 16
    • 0027878002 scopus 로고
    • Sub-59 nm gate length N-MOSFET's with 10 nm phosphorous S/D junctions
    • M. Ono et al., "Sub-59 nm gate length N-MOSFET's with 10 nm phosphorous S/D junctions," IEEE IEDM Tech.Dig., pp. 119-121, 1993
    • (1993) IEEE IEDM Tech.Dig. , pp. 119-121
    • Ono, M.1
  • 17
    • 84954096367 scopus 로고
    • Physics and technology of ultra short channel MOSFET's
    • D. A. Antoniades and J. E. Chung, "Physics and technology of ultra short channel MOSFET's," IEEE IEDM Tech. Dig., pp. 21-24, 1991.
    • (1991) IEEE IEDM Tech. Dig. , pp. 21-24
    • Antoniades, D.A.1    Chung, J.E.2
  • 18
    • 0028044343 scopus 로고    scopus 로고
    • Self-adjusted threshold voltage scheme (SATS) for low-voltage high-speed operation
    • T. Kobayashi and T. Sakurai, "Self-adjusted threshold voltage scheme (SATS) for low-voltage high-speed operation," IEEE 1994 Custom Integrated Circ. Conf., p. 271.
    • IEEE 1994 Custom Integrated Circ. Conf. , pp. 271
    • Kobayashi, T.1    Sakurai, T.2
  • 19
    • 0028013943 scopus 로고    scopus 로고
    • Limitation of CMOS supply-voltage scaling by MOSFET threshold-voltage variation
    • S. W. Sun and P. G. Y. Tsui, "Limitation of CMOS supply-voltage scaling by MOSFET threshold-voltage variation," IEEE 1994 Custom Integrated Circ. Conf., p. 267.
    • IEEE 1994 Custom Integrated Circ. Conf. , pp. 267
    • Sun, S.W.1    Tsui, P.G.Y.2
  • 20
    • 0019049847 scopus 로고
    • Design and characterization of the lightly doped drain (LDD) insulated gate field effect transistor
    • Aug.
    • S. Ogura, P. J. Tsang, W. W. Walker, D. L. Critchlow, and J. F. Shepard, "Design and characterization of the lightly doped drain (LDD) insulated gate field effect transistor," IEEE Trans. Electron Devices, vol. ED-27, pp. 1359-1367, Aug. 1980.
    • (1980) IEEE Trans. Electron Devices , vol.ED-27 , pp. 1359-1367
    • Ogura, S.1    Tsang, P.J.2    Walker, W.W.3    Critchlow, D.L.4    Shepard, J.F.5
  • 21
    • 0023310827 scopus 로고
    • The impact of intrinsic series resistance on MOSFET scaling
    • Mar.
    • K. K. Ng, and W. T. Lynch, " The impact of intrinsic series resistance on MOSFET scaling," IEEE Trans. Electron Devices, vol. ED-34, pp. 503-511, Mar. 1987.
    • (1987) IEEE Trans. Electron Devices , vol.ED-34 , pp. 503-511
    • Ng, K.K.1    Lynch, W.T.2
  • 22
    • 85008051623 scopus 로고    scopus 로고
    • A high performance 0.15 μm CMOS
    • Kyoto, Japan
    • G. G. Shahidi et al., " A high performance 0.15 μm CMOS," 1993 Symp. on VLSI Technology, Kyoto, Japan, pp. 93-94.
    • 1993 Symp. on VLSI Technology , pp. 93-94
    • Shahidi, G.G.1
  • 23
    • 30244460213 scopus 로고    scopus 로고
    • Experimental study on electron heating in 0.1 μm nMOSFET's
    • Kyoto, Japan
    • M. Dutoit et al., "Experimental study on electron heating in 0.1 μm nMOSFET's," 1993 Symp. on VLSI Tech., Kyoto, Japan, pp. 35-36.
    • 1993 Symp. on VLSI Tech. , pp. 35-36
    • Dutoit, M.1
  • 24
    • 0027879328 scopus 로고
    • High performance 0.1 μm CMOS devices with 1.5 V power supply
    • Y. Taur et al., "High performance 0.1 μm CMOS devices with 1.5 V power supply," IEDM Tech. Dig., pp. 127-130, 1993.
    • (1993) IEDM Tech. Dig. , pp. 127-130
    • Taur, Y.1
  • 26
    • 0031140867 scopus 로고    scopus 로고
    • Quantum-mechanical modeling of electron tunneling current from the inversion layer of ultr-thin-oxide nMOSFET's
    • May
    • S.-H. Lo, D. A. Buchanan, Y. Taur, and W. Wang, "Quantum-mechanical modeling of electron tunneling current from the inversion layer of ultr-thin-oxide nMOSFET's," IEEE Electron Device Letters, vol. 18, No. 5, May 1997.
    • (1997) IEEE Electron Device Letters , vol.18 , Issue.5
    • Lo, S.-H.1    Buchanan, D.A.2    Taur, Y.3    Wang, W.4
  • 31
    • 84926419270 scopus 로고
    • Shallow junctions, silicide requirements and process technologies for sub-0.5 μm CMOS
    • _, "Shallow junctions, silicide requirements and process technologies for sub-0.5 μm CMOS, " Proc. 22 ESSDERC, p. 649, 1992.
    • (1992) Proc. 22 ESSDERC , pp. 649
  • 32
    • 30244455089 scopus 로고
    • Low voltage/low power device technologies
    • B. Davari, "Low voltage/low power device technologies," IEDM Short Course, 1993.
    • (1993) IEDM Short Course
    • Davari, B.1
  • 33
    • 0024895494 scopus 로고
    • A new planarization technique, using a combination of RIE and chemical mechanical polish (CMP)
    • B. Davari et al., "A new planarization technique, using a combination of RIE and chemical mechanical polish (CMP)," IEDM Tech. Dig., pp. 61-64, 1989.
    • (1989) IEDM Tech. Dig. , pp. 61-64
    • Davari, B.1
  • 34
    • 0026105523 scopus 로고
    • Comparison of transformation to low-resistivity phase and agglomeration of TiSi2 and CoSi2
    • Feb.
    • J. B. Lasky, J. S. Nakos, O. J. Cain, and P. J. Geiss, "Comparison of transformation to low-resistivity phase and agglomeration of TiSi2 and CoSi2," IEEE Trans. Electron Devices, vol. ED-38, pp. 262-269, Feb. 1991.
    • (1991) IEEE Trans. Electron Devices , vol.ED-38 , pp. 262-269
    • Lasky, J.B.1    Nakos, J.S.2    Cain, O.J.3    Geiss, P.J.4
  • 35
    • 30244484300 scopus 로고
    • Metal-oxide-semiconductor field effect devices for micropower logic circuitry
    • E. Keonjian, Ed. London/New York: Pergamon
    • G. Moore et al., "Metal-oxide-semiconductor field effect devices for micropower logic circuitry," Micropower Electronics, E. Keonjian, Ed. London/New York: Pergamon, 1964
    • (1964) Micropower Electronics
    • Moore, G.1
  • 36
    • 85056911965 scopus 로고
    • Monte Carlo simulation of a 30 nm dual gate mosfet: How short can Si go?
    • D. J. Frank et al., "Monte Carlo simulation of a 30 nm dual gate mosfet: How short can Si go?" IEEE IEDM Dig. Papers, pp. 553-556, 1992.
    • (1992) IEEE IEDM Dig. Papers , pp. 553-556
    • Frank, D.J.1
  • 37
  • 38
    • 0027641506 scopus 로고
    • Indium channel implant for improved short-channel behavior of submicrometer nMOSFETs
    • Aug.
    • G. G. Shahidi et al., "Indium channel implant for improved short-channel behavior of submicrometer nMOSFETs," IEEE Electron Device Lett., vol. 14, pp. 409-411, Aug. 1993
    • (1993) IEEE Electron Device Lett. , vol.14 , pp. 409-411
    • Shahidi, G.G.1
  • 39
    • 0029702277 scopus 로고    scopus 로고
    • A 0.25 μm gate length CMOS technology for IV low power applications-device design and power/performance considerations
    • M. Nandakumar, A. Chatterjee, G. Stacey, and I.-C. Chen, "A 0.25 μm gate length CMOS technology for IV low power applications-device design and power/performance considerations," Symp. on VLSI Tech. Dig., pp. 68-69, 1996.
    • (1996) Symp. on VLSI Tech. Dig. , pp. 68-69
    • Nandakumar, M.1    Chatterjee, A.2    Stacey, G.3    Chen, I.-C.4
  • 40
    • 0029544326 scopus 로고    scopus 로고
    • A device design study of 0.25 μm gate length CMOS for 1V low power applications
    • M. Nandakumar, A. Chatterjee, G. Stacey, and I.-C. Chen, "A device design study of 0.25 μm gate length CMOS for 1V low power applications," 1995 IEEE Proc., pp. 80-81.
    • 1995 IEEE Proc. , pp. 80-81
    • Nandakumar, M.1    Chatterjee, A.2    Stacey, G.3    Chen, I.-C.4
  • 41
    • 0029723467 scopus 로고    scopus 로고
    • High-frequency characteristics and its dependence on parasitic components in 0.1 μm Si-MOSFET's
    • T. Yamamoto, A. Tanabe, M. Togo, A. Furukawa, and T. Mogami, "High-frequency characteristics and its dependence on parasitic components in 0.1 μm Si-MOSFET's, Symp. on VLSI Tech. Dig., pp. 136-137, 1996.
    • (1996) Symp. on VLSI Tech. Dig. , pp. 136-137
    • Yamamoto, T.1    Tanabe, A.2    Togo, M.3    Furukawa, A.4    Mogami, T.5
  • 45
    • 0028754970 scopus 로고
    • Low threshold voltage CMOS devices with smooth topography for 1Volt applications
    • D. C. H. Yu, H. D. Lin, C. McAndrew, and K. H. Lee, "Low threshold voltage CMOS devices with smooth topography for 1Volt applications," IEDM Tech. Dig., pp. 489-492, 1994.
    • (1994) IEDM Tech. Dig. , pp. 489-492
    • Yu, D.C.H.1    Lin, H.D.2    McAndrew, C.3    Lee, K.H.4
  • 46
    • 4243081808 scopus 로고
    • A non-uniformly doped channel (NUDC) MOSFET
    • Y. Okumura et al., "A non-uniformly doped channel (NUDC) MOSFET," IEDM Tech. Dig., p. 391, 1990
    • (1990) IEDM Tech. Dig. , pp. 391
    • Okumura, Y.1
  • 48
    • 0029520355 scopus 로고
    • A high performance 0.1 μm MOSFET with asymmetric channel profile
    • A. Hiroki, S. Odanaka, and A. Hori, "A high performance 0.1 μm MOSFET with asymmetric channel profile," IEDM Tech. Dig., pp. 439-442, 1995.
    • (1995) IEDM Tech. Dig. , pp. 439-442
    • Hiroki, A.1    Odanaka, S.2    Hori, A.3


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.