0.25 μm gate length CMOS technology for 1V low power applications - device design and power/performance considerations

Digest of Technical Papers - Symposium on VLSI Technology

Volumn , Issue , 1996, Pages 68-69

  Nandakumar, M ^a   Chatterjee, A ^a   Stacey, G ^a   Chen, I C ^a  

^a TEXAS INSTRUMENTS   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

ELECTRIC CURRENTS; ELECTRIC INVERTERS; ELECTRIC RESISTANCE; GATES (TRANSISTOR); INTEGRATED CIRCUIT LAYOUT; SEMICONDUCTOR DOPING; SWITCHING;

COUNTERDOPED SUPER STEEP RETROGRADE CHANNEL; GATE LENGTH CONTROL; GATE SHEET RESISTANCE;

CMOS INTEGRATED CIRCUITS;

EID: 0029702277     PISSN: 07431562     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (7)