Device design study of 0.25μm gate length CMOS for 1V low power applications

IEEE Symposium on Low Power Electronics

Volumn , Issue , 1995, Pages 80-81

  Nandakumar, M ^a   Chatterjee, A ^a   Rodder, M ^a   Chen, I C ^a  

^a TEXAS INSTRUMENTS   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

CMOS INTEGRATED CIRCUITS; COMPUTER SIMULATION; CURRENT VOLTAGE CHARACTERISTICS; ELECTRIC INVERTERS; ELECTRIC POWER SUPPLIES TO APPARATUS; INTEGRATED CIRCUIT MANUFACTURE; LEAKAGE CURRENTS; SEMICONDUCTOR DOPING; VLSI CIRCUITS;

CHANNEL PROFILES; COUNTER DOPING; LOW POWER APPLICATIONS; SOFTWARE PACKAGE SPICE;

INTEGRATED CIRCUIT LAYOUT;

EID: 0029544326     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (8)