A high performance 0.15 μm CMOS

Digest of Technical Papers - Symposium on VLSI Technology

Volumn , Issue , 1993, Pages 93-94

  Shahidi, G G ^a   Warnock, J ^a   Acovic, A ^a   Agnello, P ^a   Blair, C ^a   Bucelot, T ^a   Burghartz, A ^a   Crabbe, E ^a   Cressler, J ^a   Coane, P ^a   Comfort, J ^a   Davari, B ^a   Fischer, S ^a   Ganin, E ^a   Gittleman, S ^a   Keller, J ^a   Jenkins, K ^a   Klaus, D ^a   Kiewtniak, K ^a   Lii, T ^a   McFarland, P A ^a   Ning, T ^a   Polcari, M ^a   Subbana, S ^a   Sun, J Y ^a   Sunderland, D ^a   Warren, A C ^a   Wong, C ^a   more..

^a IBM T J WATSON RESEARCH CENTER   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

VLSI CIRCUITS;

CHANNEL DOPINGS; CHANNEL LENGTH; CMOS TECHNOLOGY; NON-UNIFORM; SHORT-CHANNEL EFFECT; SOURCE-DRAIN EXTENSIONS; STACK GATE STRUCTURE; SUPPLY VOLTAGES;

CMOS INTEGRATED CIRCUITS;

EID: 85008051623     PISSN: 07431562     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/VLSIT.1993.760261     Document Type: Conference Paper

References (2)

1. B. Davari et al, IEDM Tech. Dig., p. 56 (1988).
2. G. Shahidi et al, Submitted to IEEE EDL.