High-performance sub-0.1-μm CMOS with low-resistance T-shaped gates fabricated by selective CVD-W

Digest of Technical Papers - Symposium on VLSI Technology

Volumn , Issue , 1995, Pages 115-116

  Hisamoto, D ^a   Umeda, K ^a   Nakamura, Y ^a   Kobayashi, N ^a   Kimura, S ^a   Nagai, R ^a  

^a HITACHI LTD   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

CALCULATIONS; CHEMICAL VAPOR DEPOSITION; CURRENT VOLTAGE CHARACTERISTICS; ELECTRIC RESISTANCE; GATES (TRANSISTOR); OSCILLATORS (ELECTRONIC); PERFORMANCE; SEMICONDUCTOR DEVICE MANUFACTURE; SEMICONDUCTOR DEVICE STRUCTURES; SEMICONDUCTOR DOPING; SEMICONDUCTOR GROWTH; TUNGSTEN;

COUNTER DOPING; LOW-RESISTANCE T-SHAPED GATES; RING-OSCILLATOR GATE-DELAY TIME; SELECTIVE CHEMICAL VAPOR DEPOSITION; THRESHOLD VOLTAGE SCALING; TUNGSTEN GROWTH;

CMOS INTEGRATED CIRCUITS;

EID: 0029512252     PISSN: 07431562     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (5)