Ultra-thin SOI CMOS with selective CVD tungsten for low-resistance source and drain

Technical Digest - International Electron Devices Meeting, IEDM

Volumn 1992-December, Issue , 1992, Pages 829-832

  Hisamoto, D ^a   Nakamura, K ^a   Saito, M ^a   Kobayashi, N ^a   Kimura, S ^a   Nagai, R ^a   Nishida, T ^a   Takeda, E ^a  

^a HITACHI LTD   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

ELECTRON DEVICES; SILICON COMPOUNDS; TUNGSTEN;

CMOS DEVICES; CONTACT CHARACTERISTICS; DEVICE PERFORMANCE; DIFFUSION LAYERS; LOW RESISTANCE; LOW-PARASITIC; SOURCE AND DRAINS; ULTRA-THIN;

CMOS INTEGRATED CIRCUITS;

EID: 33747713759     PISSN: 01631918     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/IEDM.1992.307485     Document Type: Conference Paper

References (7)

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2. Y. Omura, S. Nakashima, K. Izumi and T. Ishii, "0. 1-um-gate Ulirathin-Film CMOS Devices Using SIMOX Subsirate wilh 80-nm-lhick Buried Oxide Layer, " in IEDM Tech. Dig., pp. 675-678, 1991.
3. D. Hisamoto, T. Kaga and E. Takcda, "Impact of die Vertical SOI 'DELTA' Structure on Planar Device Technology, " IEEE Trans. Electon Devices, vol. 38, no. 6, pp. 1419-1424, 1991.
4. C.-Y. Lu ct al., "Process Limitation and Device Design Tradeoffs of Self-Aligned TiSij Junction Formation in Submicromctcr CMOS Devices, " IEEE Trans. Electron Devices, vol, 38, no. 2, pp. 246-254, 1991.
5. Y. Kusumoto, K. Takakuwa, II. Hashinouchi, T. Dcuta and I. Nakayama, "A New Approach to the Suppression of Tunneling, " Tungsten and other Refractory Metals for VLSI Applications, pp. 103-109, 1987.
6. T. Ohba, S. Inoue and M. Maeda, "Selective CVD Tungsten Silicide for VLSI Applications. " in IEDM Tech. Dig., pp. 213-216, 1987.
7. H. Kotani, T. Tsulsumi, J. Komori and S. Nagao, "A Highly Reliable Selective CVD-W utilizing Sill, Reduction for VLSI Contacts, " in IEDM Tech. Dig., pp. 217-220, 1987.