Self-aligned tungsten strapped source/drain and gate technology realizing the lowest sheet resistance for sub-quarter micron CMOS

Technical Digest - International Electron Devices Meeting

Volumn , Issue , 1994, Pages 493-496

  Sekine, M ^a   Inoue, K ^a   Ito, H ^a   Honma, I ^a   Miyamoto, H ^a   Yoshida, K ^a   Watanabe, H ^a   Mikagi, K ^a   Yamada, Y ^a   Kikkawa, T ^a  

^a NEC CORPORATION   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

ANNEALING; CHEMICAL VAPOR DEPOSITION; DIFFUSION IN SOLIDS; ELECTRIC RESISTANCE; ETCHING; FABRICATION; GATES (TRANSISTOR); INTEGRATED CIRCUIT MANUFACTURE; ION IMPLANTATION; NUCLEATION; SEMICONDUCTOR DEVICE STRUCTURES; TUNGSTEN;

SHEET RESISTANCE; SUBQUARTER MICRON CMOS;

CMOS INTEGRATED CIRCUITS;

EID: 0028737006     PISSN: 01631918     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (5)