-
1
-
-
0022027064
-
-
IEEE Trans. Electron Devices, vol. ED-32, p. 584, 1985.
-
G. J. Hu and R. H. Bruce, Design tradeoffs between surface and buriedchannel FET's, IEEE Trans. Electron Devices, vol. ED-32, p. 584, 1985.
-
Design Tradeoffs between Surface and Buriedchannel FET's
-
-
Hu, G.J.1
Bruce, R.H.2
-
2
-
-
0039956433
-
-
IEEE Electron Device Lett., vol. EDL-1, p. 2, 1980.
-
J. R. Brews, W. Fichtner, E. H. Nicollian, and S. M. Sze, Generalized guide for MOSFET miniaturization, IEEE Electron Device Lett., vol. EDL-1, p. 2, 1980.
-
Generalized Guide for MOSFET Miniaturization
-
-
Brews, J.R.1
Fichtner, W.2
Nicollian, E.H.3
Sze, S.M.4
-
5
-
-
0025486395
-
-
IEEE Trans. Electron Devices, vol. 37, p. 2007, 1990.
-
M. Miyake, T. Kobayashi, and Y. Okazakj, Subquarter-micrometer gate-length p-channel MOSFET's with shallow boron counter-doped layer fabricated using channel preamorphization, IEEE Trans. Electron Devices, vol. 37, p. 2007, 1990.
-
Subquarter-micrometer Gate-length P-channel MOSFET's with Shallow Boron Counter-doped Layer Fabricated Using Channel Preamorphization
-
-
Miyake, M.1
Kobayashi, T.2
Okazakj, Y.3
-
6
-
-
0028744296
-
-
IEDM Tech. Dig. 1994, p. 683, 1994.
-
T. Kobayashi, S. Nakayama, M. Miyake, and Y. Okazaki, Nitrogen insitu doped poly buffer LOCOS: Simple and scalable isolation technology for deep-submicron devices, IEDM Tech. Dig. 1994, p. 683, 1994.
-
Nitrogen Insitu Doped Poly Buffer LOCOS: Simple and Scalable Isolation Technology for Deep-submicron Devices
-
-
Kobayashi, T.1
Nakayama, S.2
Miyake, M.3
Okazaki, Y.4
-
7
-
-
0024106862
-
-
J. Electrochem. Soc., vol. 135, p. 2872, 1988.
-
M. Miyake, S. Aoyama, S. Hirota, and T. Kobayashi. Properties of preamorphized and rapid thermal annealed shallow p+n junctions, J. Electrochem. Soc., vol. 135, p. 2872, 1988.
-
Properties of Preamorphized and Rapid Thermal Annealed Shallow P+n Junctions
-
-
Miyake, M.1
Aoyama, S.2
Hirota, S.3
Kobayashi, T.4
-
8
-
-
0024610567
-
-
IEEE Trans. Electron Devices, vol. 36, p. 392, 1989.
-
M. Miyake, T. Kobayashi, and Y. Okazaki, Subquarter-micrometer gatelength p-channel and n-channel MOSFET's with extremely shallow source-drain junctions, IEEE Trans. Electron Devices, vol. 36, p. 392, 1989.
-
Subquarter-micrometer Gatelength P-channel and N-channel MOSFET's with Extremely Shallow Source-drain Junctions
-
-
Miyake, M.1
Kobayashi, T.2
Okazaki, Y.3
-
9
-
-
0021408231
-
-
J. Electrochem. Soc., vol. 131, p. 943, 1984.
-
D. K. Sadana, W. Maszara, J. 1. Wortman, G. A. Rozgonyi, and W. K. Chu, Germanium implantation into silicon, J. Electrochem. Soc., vol. 131, p. 943, 1984.
-
Germanium Implantation into Silicon
-
-
Sadana, D.K.1
Maszara, W.2
Wortman, J.I.3
Rozgonyi, G.A.4
Chu, W.K.5
-
10
-
-
85176517734
-
-
J. Appl. Phys., vol. 60, p. 3567, 1986.
-
S. D. Brotherton, J. P. Cowers, N. D. Young, J. B. Clegg, and J. R. Ayres, Defects and leakage currents in BF2 implanted preamorphizetl silicon, J. Appl. Phys., vol. 60, p. 3567, 1986.
-
Defects and Leakage Currents in BF2 Implanted Preamorphizetl Silicon
-
-
Brotherton, S.D.1
Cowers, J.P.2
Young, N.D.3
Clegg, J.B.4
Ayres, J.R.5
-
11
-
-
0025577128
-
-
IEDM Tech. Dig. 1990, p. 405, 1990.
-
H. Uchida, I. Aikawa, N. Hirashita, and T. Ajioka, Enhanced degradation of oxide breakdown in the peripheral region by metallic contamination, IEDM Tech. Dig. 1990, p. 405, 1990.
-
Enhanced Degradation of Oxide Breakdown in the Peripheral Region by Metallic Contamination
-
-
Uchida, H.1
Aikawa, I.2
Hirashita, N.3
Ajioka, T.4
-
12
-
-
0020797242
-
-
IEEE Trans. Electron Devices, vol. ED-30, p. 871, 1983.
-
K. K. Ng and G. W. Taylor, Effects of hot-carrier trapping ill n- and p-channel MOSFET's, IEEE Trans. Electron Devices, vol. ED-30, p. 871, 1983.
-
Effects of Hot-carrier Trapping Ill N- and P-channel MOSFET's
-
-
Ng, K.K.1
Taylor, G.W.2
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