Device Design for the Submicrometer p-Channel FET with n+ Polysilicon gate

IEEE Transactions on Electron Devices

Volumn 31, Issue 7, 1984, Pages 964-968

  Cham, Kit M ^a   Chiang, Shang Yi ^a  

^a HEWLETT PACKARD LABORATORIES   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

INTEGRATED CIRCUITS, VLSI - MANUFACTURE; SEMICONDUCTING SILICON - APPLICATIONS;

POLYSILICON GATE; SUBMICROMETER P-CHANNEL FET; VLSI CMOS;

TRANSISTORS, FIELD EFFECT;

EID: 0021453025     PISSN: 00189383     EISSN: 15579646     Source Type: Journal    
DOI: 10.1109/T-ED.1984.21638     Document Type: Article

References (9)

1. E. Takeda, Y. Nakagome, H. Kume, N. Suzuki, and S. Asai, “Coin-parison of characteristics of n-channel and p-channel MOSFET’s for VLSI’s,” IEEE Trans. Electron Devices, vol. ED-30, no. 6, pp. 675–-680 June 1983.
2. L. C. Thomas and J. J. Molinelli, “VLSI Logic,” in ISSCC Dig, Tech. Papers, pp. 230–231, Feb. 1981.
3. L. C. Parrillo, L. K. Wang, R. D. Swenumson, R. L. Field, R. C. Melin, and R. A. Levy, “Twin-tub CMOS II-An advanced VLSI technology,” in IEDM Tech. Dig., pp. 706-709,1982.
4. J. A. Greenfield and R. W. Dutton, “Nonplanar VLSI device analysis using the solution of the Poisson’s equation,” IEEE Trans. Electron Devices, vol. ED-27, no. 8, 1520–1532, Aug. 1980.
5. R. R. Troutman, “VLSI limitions from drain-induced barrier lowering,” IEEE Trans. Electron Devices, vol. ED-26, no. 4, pp. 461—468, 1979.
6. R. R. Troutman, “Subthreshold slope for insulated gate field-effect transistors,” IEEE Trans. Electron Devices, vol. ED-22, no. 11, pp. 1049–1051
7. G. J. Hu, C. Y. Ting, Y. Taur, and R. H. Dennard, “Design and fabrication of p-channel FET for 1-μm CMOS technology,” in IEDM Tech. Dig., 1982.
8. M. Y. Tsai and B. G. Streetman, “Recrystallization of implanted amorphous silicon layers. I. Electrical properties of silicon implanted with BF2 or Si+ + B+,” J. Appl. Phys., vol. 50, pp. 183, 1979.
9. W. Jost, Diffusion in Solids, Liquids, Gases. New York: Academic, 1952.