Design Tradeoffs Between Surface and Buried-Channel FET's

IEEE Transactions on Electron Devices

Volumn 32, Issue 3, 1985, Pages 584-588

  Hu, Genda J ^a   Bruce, Richard H ^b  

^a Device Engineering Department Sierra Semiconductor Corporation ^*  (United States)

^b PALO ALTO RESEARCH CENTER   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

SEMICONDUCTOR MATERIALS - DOPING;

BURIED-CHANNEL DEVICES; DESIGN TRADEOFFS; DOPING CONCENTRATIONS; N-TYPE POLYSILICON GATES; SURFACE-CHANNEL DEVICES;

TRANSISTORS, FIELD EFFECT;

EID: 0022027064     PISSN: 00189383     EISSN: 15579646     Source Type: Journal    
DOI: 10.1109/T-ED.1985.21981     Document Type: Article

References (12)

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12. K. Cham and S. Chaing, “Device design for the submicrometer p-channel FET with n+ polysilicon gate,” IEEE Trans. Electron Devices, vol. ED-31, p. 964, 1984