-
1
-
-
0032272375
-
Ultra-thin gate oxides - performance and reliability
-
Iwai H, Momose HS. Ultra-thin gate oxides - performance and reliability. IEDM'98, 1998.
-
(1998)
IEDM'98
-
-
-
2
-
-
0032628950
-
The incredible shrinking transistor
-
Taur Y. The incredible shrinking transistor. IEEE Spectrum 1999;7:25-9.
-
(1999)
IEEE Spectrum
, vol.7
, pp. 25-29
-
-
Taur, Y.1
-
4
-
-
0033343947
-
Gate oxides in 50 nm devices: Thickness uniformity improves projected reliability
-
Weir BE, Silverman PJ, Alam MA, Baumann F, Monroe D, Ghetti A, Bude JD, Timp GL, Hamad A, Oberdick TM, Zhao NX, Ma Y, Brown MM, Hwang D, Sorsch TW, Madic J. Gate oxides in 50 nm devices: thickness uniformity improves projected reliability. IEEE IEDM, 1999:437.
-
(1999)
IEEE IEDM
, pp. 437
-
-
Weir, B.E.1
Silverman, P.J.2
Alam, M.A.3
Baumann, F.4
Monroe, D.5
Ghetti, A.6
Bude, J.D.7
Timp, G.L.8
Hamad, A.9
Oberdick, T.M.10
Zhao, N.X.11
Ma, Y.12
Brown, M.M.13
Hwang, D.14
Sorsch, T.W.15
Madic, J.16
-
5
-
-
0000010540
-
Reactionannealing pathways for forming ultrathin silicon nitride films for composite oxide nitride gate dielectrics with nitrided crystalline silicon-dielectric interfaces for application in advanced complementary MOS devices
-
Lucovsky G. Reactionannealing pathways for forming ultrathin silicon nitride films for composite oxide nitride gate dielectrics with nitrided crystalline silicon-dielectric interfaces for application in advanced complementary MOS devices. J Vac Sci Technol A. 17(4):1999;1340.
-
(1999)
J Vac Sci Technol a
, vol.17
, Issue.4
, pp. 1340
-
-
Lucovsky, G.1
-
6
-
-
0032024519
-
Making silicon nitride film a viable gate dielectric
-
Ma T.P. Making silicon nitride film a viable gate dielectric. IEEE Trans Electron Dev. 45(3):1998;680.
-
(1998)
IEEE Trans Electron Dev
, vol.45
, Issue.3
, pp. 680
-
-
Ma, T.P.1
-
7
-
-
85031568434
-
-
58th Device Research Conference, Denver, Colorado, 19-21 June
-
Zhang J, Yuan JS, Ma Y, Oates AS. Design optimization of stacked high-k dielectrics using a convenient evaluation of gate leakage current in deep submicron MOSFET. 58th Device Research Conference, Denver, Colorado, 19-21 June, 2000.
-
(2000)
Design Optimization of Stacked High-k Dielectrics Using a Convenient Evaluation of Gate Leakage Current in Deep Submicron MOSFET
-
-
Zhang, J.1
Yuan, J.S.2
Ma, Y.3
Oates, A.S.4
-
8
-
-
0031144288
-
Preventing boron penetration through 25-A gate oxides with nitrgen implant in the Si substrates
-
Liu CT, Ma Y, Luftman H, Hillenius SJ. Preventing boron penetration through 25-A gate oxides with nitrgen implant in the Si substrates. IEEE Elec Dev Lett 1997;18(5):212.
-
(1997)
IEEE Elec Dev Lett
, vol.18
, Issue.5
, pp. 212
-
-
Liu, C.T.1
Ma, Y.2
Luftman, H.3
Hillenius, S.J.4
-
9
-
-
0032655915
-
The impact of high-k gate dielectrics and metal gate electrodes on sub-100 nm MOSFETs
-
Cheng B., Cao M., Rao R., Inani A., Voorde P.V., Greene W.M., Stork J.M.C., Yu Z., Zeitzoff P.M., Woo J.C.S. The impact of high-k gate dielectrics and metal gate electrodes on sub-100 nm MOSFETs. IEEE Trans Electron Dev. 46(7):1999;1537.
-
(1999)
IEEE Trans Electron Dev
, vol.46
, Issue.7
, pp. 1537
-
-
Cheng, B.1
Cao, M.2
Rao, R.3
Inani, A.4
Voorde, P.V.5
Greene, W.M.6
Stork, J.M.C.7
Yu, Z.8
Zeitzoff, P.M.9
Woo, J.C.S.10
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