Analysis of the design space available for high-k gate dielectrics in nanoscale MOSFETs

Superlattices and Microstructures

Volumn 28, Issue 5-6, 2000, Pages 485-491

  Frank, David J ^a   Wong, Hon Sum P ^a  

^a IBM T J WATSON RESEARCH CENTER   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

CMOS INTEGRATED CIRCUITS; DIELECTRIC MATERIALS; ELECTRIC INSULATORS; GATES (TRANSISTOR); NANOSTRUCTURED MATERIALS; PERMITTIVITY; SEMICONDUCTOR DEVICE MODELS;

DOABLE GATE MOSFET; HIGH GATE DIELECTRICS; SCALING;

MOSFET DEVICES;

EID: 0034318593     PISSN: 07496036     EISSN: None     Source Type: Journal    
DOI: 10.1006/spmi.2000.0952     Document Type: Article

References (5)

1. Taur et al. Y. CMOS scaling into the nanometer regime. Proc. IEEE. 85:1997;486.
2. 2at low voltage, 2000 Symposium on VLST Technology, Honolulu, Published for IEEE by Widerkehr and Assoc., Gaithersbury, MD. 2000;. p. 94-95.
3. Yeap G.-F., Krishnan S., Lin M.-R. Fringing induced barrier lowering (FIBL) in sub 100 nm MOSFETs with high-k gate dielectrics. Electron. Lett. 34:1998;1150.
4. Frank D., Taur Y., Wong H.-S. P. Generalized scale length for two-dimensional effects in MOSFET's. IEEE Electron Device Lett. 19:1998;385.
5. Buturla E., Johnson J., Furkay S., Cottrell P. A new 3-D device simulation formulation, NASCODE VI. 1989;. p. 291.