A 40-43-Gb/s Clock and Data Recovery IC with Integrated SFI-5 1:16 Demultiplexer in SiGe Technology

IEEE Journal of Solid-State Circuits

Volumn 38, Issue 12, 2003, Pages 2155-2168

  Ong, Adrian ^a   Benyamin, Saied ^a   Cancio, Jason ^a   Condito, Vincent ^a   Labrie, Tad ^a   Lee, Qinghung ^a   Mattia, John Paul ^a,b   Shaeffer, Derek K ^a,c   Shahani, Arvin ^a,c   Si, Xiaomin ^a   Tao, Hai ^a   Tarsia, Maurice ^a   Wong, Wayne ^a   Xu, Min ^a  

^a Big Bear Networks   (United States)

^b Tarkus Consulting   (United States)

^c Aspendos Communications   (United States)

Author keywords

Bang bang; Charge pump; Clock and data recovery (CDR); Demultiplexer; Jitter tolerance; OC 768; Optical fiber communication; Phase detector; SFI 5; SiGe; SONET; Voltage controlled oscillator (VCO)

Indexed keywords

AMPLIFIERS (ELECTRONIC); BANG BANG CONTROL SYSTEMS; DEMULTIPLEXING; ERROR CORRECTION; JITTER; MODULATORS; OPTICAL COMMUNICATION; OSCILLATORS (ELECTRONIC); PHOTODIODES; POWER SUPPLY CIRCUITS; ROBUSTNESS (CONTROL SYSTEMS); SIGNAL NOISE MEASUREMENT; SILICON COMPOUNDS; TRANSPONDERS; VOLTAGE CONTROL;

CHARGE PUMPS; JITTER TOLERANCE; OPTICAL FIBER COMMUNICATION; PHASE DETECTORS; VOLTAGE CONTROLLED OSCILLATORS (VCO);

INTEGRATED CIRCUITS;

EID: 9144269955     PISSN: 00189200     EISSN: None     Source Type: Journal    
DOI: 10.1109/JSSC.2003.818565     Document Type: Conference Paper

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