Clock and data recovery IC for 40-Gb/s fiber-optic receiver

IEEE Journal of Solid-State Circuits

Volumn 37, Issue 9, 2002, Pages 1120-1125

  Georgiou, George ^a,b   Baeyens, Yves ^a,b   Chen, Young Kai ^a,b   Gnauck, Alan H ^a,b   Cropper, Garsten ^c   Paschke, Peter ^c   Pullela, Rajasekhar ^c,d   Reinhold, Mario ^e   Dorschky, Claus ^e   Mattia, John Paul ^f   Von Mohrenfels, Timo Winkler ^e   Schuhen, Christoph ^e  

^a IEEE   (United States)

^b LUCENT TECHNOLOGIES   (United States)

^c NOKIA RESEARCH CENTER   (United States)

^d Gtran Inc   (United States)

^e Core Optics ^*  (Germany)

^f Big Bear Networks   (United States)

Author keywords

CDR; Clock and data recovery; Fiber optic communication receiver; InP HBT; Limiting amplifier; Phase detector; VCO

Indexed keywords

CLOCK AND DATA RECOVERY; DEMULTIPLEXER; DIGITAL PHASE DETECTOR; FIBER OPTIC RECEIVER;

BUFFER AMPLIFIERS; FREQUENCY DIVIDING CIRCUITS; FREQUENCY MULTIPLYING CIRCUITS; HETEROJUNCTION BIPOLAR TRANSISTORS; INTEGRATED CIRCUIT LAYOUT; INTEGRATED CIRCUIT MANUFACTURE; LIMITERS; OPTICAL COMMUNICATION EQUIPMENT; PHASE LOCKED LOOPS; SEMICONDUCTING INDIUM PHOSPHIDE; VARIABLE FREQUENCY OSCILLATORS;

BIPOLAR INTEGRATED CIRCUITS;

EID: 0036712287     PISSN: 00189200     EISSN: None     Source Type: Journal    
DOI: 10.1109/JSSC.2002.801186     Document Type: Conference Paper

References (8)

1. Packaged clock recovery integrated circuits for 40-Gb/s optical communication links
2. T silicon bipolar technology
3. A plastic packaged 10-Gb/s BiCMOS clock and data recovering 1:4 demultiplexer with external VCO
4. A fully integrated 40-Gb/s clock and data recovery/1 : 4 DEMUX IC in SiGe technology
5. Clock recovery from random binary signals
6. Design considerations for very high speed Si-bipolar ICs operating up to 50 Gb/s
7. A low power 52.9-GHz static divider implemented in a manufacturable 180-GHz inAlAs/InGaAs HBT IC technology
8. High gain limiting amplifier for 10-Gb/s lightwave receivers