SiGe BiCMOS 3.3-V clock and data recovery circuits for 10-Gb/s serial transmission systems

IEEE Journal of Solid-State Circuits

Volumn 35, Issue 12, 2000, Pages 1992-1995

  Meghelli, Mounir ^a   Parker, Ben ^a   Ainspan, Herschel ^a   Soyuer, Mehmet ^a  

^a IBM T J WATSON RESEARCH CENTER   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

BANDWIDTH; OPTICAL FIBERS; PHASE LOCKED LOOPS; VARIABLE FREQUENCY OSCILLATORS;

ETHERNET; MONOLITHIC CLOCKS; PHASE DETECTORS; SERIAL TRANSMISSION SYSTEMS;

CMOS INTEGRATED CIRCUITS;

EID: 0034482511     PISSN: 00189200     EISSN: None     Source Type: Journal    
DOI: 10.1109/4.890314     Document Type: Article

References (8)

1. IEEE 802.3 Higher Speed Study Group. (2000, Jan.) 10Gb/s Ethernet Project. [Online]. Available: http://grouper.ieee.org/groups/ 802/3/10G_study/public
2. T. Morikawa, et al., "A SiGe single-chip 3.3-V receiver IC for 10-Gb/s optical communication systems," in Proc. ISSCC, 1999, pp. 380-381.
3. Y. M. Greshishchev, et al., "SiGe clock and data recovery IC with linear type PLL for 10-Gb/s SONET application," in BCTM Proc., 1999, pp. 169-172.
4. R. C. Walker, K.-C. Hsieh, T. A. Knotts, and C.-S. Yen, "A 10-Gb/s Si-bipolar TX/RX chipset for computer data transmission," in Proc. ISSCC, 1998, pp. 302-303.
5. J. Hauenschild, et al., "A plastic packaged 10-Gb/s BiCMOS clock and data recovering 1:4-demultiplexer with external VCO," IEEE J. Solid-State Circuits, vol. 31, pp. 2056-2059, Dec. 1996.
6. IBM. SiGe technology for telecommunications and mixed signal applications. [Online]. Available: http://www.chips.ibm.com/bluelogic/ showcase/sige/whitepaper.html
7. T. H. Lee, et al., "A 155-MHz clock recovery delay-and phase-locked loop," IEEE J. Solid-State Circuits, vol. 27, pp. 1736-1746, Dec. 1992.
8. J. F. Ewen, et al., "CMOS circuits for Gb/s serial data communication," IBM J. Res. Dev., pp. 73-81, Jan./Mar. 1995.