A 10-Gb/s CDR/DEMUX with LC delay line VCO in 0.18-μm CMOS

IEEE Journal of Solid-State Circuits

Volumn 37, Issue 12, 2002, Pages 1781-1789

  Rogers, Jonathan E ^a,b   Long, John R ^a,c  

^a UNIVERSITY OF TORONTO   (Canada)

^b Inphi Corporation   (United States)

^c DELFT UNIVERSITY OF TECHNOLOGY   (Netherlands)

Author keywords

Bang bang phase locked loop; Clock and data recovery; LC delay line; Phase detector; SONET OC 192; Voltage controlled oscillator

Indexed keywords

CMOS INTEGRATED CIRCUITS; DEMULTIPLEXING; ELECTRIC DELAY LINES; GAIN CONTROL; JITTER; PHASE LOCKED LOOPS; SIGNAL TO NOISE RATIO; VARIABLE FREQUENCY OSCILLATORS;

DELAY LINE OSCILLATORS;

TELECOMMUNICATION NETWORKS;

EID: 0036917748     PISSN: 00189200     EISSN: None     Source Type: Journal    
DOI: 10.1109/JSSC.2002.804337     Document Type: Conference Paper

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