-
1
-
-
85036619319
-
Systems-on-a-chip
-
“Systems-on-a-chip,” in IEEE Int. Solid-State Circuits Conf. (ISSCCl 1996).
-
(1996)
IEEE Int
-
-
-
6
-
-
0003915801
-
-
Electronics Research Lab., Univ. Calif., Berkeley, Memo UCB/ERL M520, May
-
L. Nagel, “SPICE2: A computer program to simulate semiconductor circuits,” Electronics Research Lab., Univ. Calif., Berkeley, Memo UCB/ERL M520, May 1975.
-
(1975)
SPICE2: A Computer Program to Simulate Semiconductor Circuits
-
-
Nagel, L.1
-
7
-
-
0029719538
-
Synthesis tools for mixed-signal ICs: Progress on frontend and backend strategies
-
L. R. Carley, G. Gielen, R. Rutenbar, and W. Sansen, “Synthesis tools for mixed-signal ICs: Progress on frontend and backend strategies,” in Proc. ACM/IEEE Design Automation Conf (DAC), 1996, pp. 298-303.
-
(1996)
Proc. ACM/IEEE Design Automation Conf (DAC)
, pp. 298-303
-
-
Carley, L.R.1
Gielen, G.2
Rutenbar, R.3
Sansen, W.4
-
10
-
-
0024908745
-
OASYS: A framework for analog circuit synthesis
-
R. Harjani, R. Rutenbar, and L. R. Carley, “OASYS: A framework for analog circuit synthesis,” IEEE Trans. Computer-Aided Design, vol. 8, pp. 1247-1265, Dec. 1989.
-
(1989)
IEEE Trans. Computer-Aided Design
, vol.8
, pp. 1247-1265
-
-
Harjani, R.1
Rutenbar, R.2
Carley, L.R.3
-
11
-
-
25844512528
-
Open analog synthesis system based on declarative models
-
J. Huijsing, R. van der Plassche, and W. Sansen, Eds. Norwell, MA: Kluwer
-
G. Gielen, K. Swings, and W. Sansen, “Open analog synthesis system based on declarative models.” in Analog Circuit Design, J. Huijsing, R. van der Plassche, and W. Sansen, Eds. Norwell, MA: Kluwer, 1993, pp. 421-445.
-
(1993)
Analog Circuit Design
, pp. 421-445
-
-
Gielen, G.1
Swings, K.2
Sansen, W.3
-
13
-
-
6144262763
-
A top-down, constraint-driven design methodology for analog integrated circuits
-
H. Chang et al, “A top-down, constraint-driven design methodology for analog integrated circuits,” in Proc. IEEE Custom Integrated Circuits Conf C/CO. 1992, pp. 8.4.1-8.4.6.
-
(1992)
Proc. IEEE Custom Integrated Circuits Conf (C/CO
, pp. 1-8
-
-
Chang, H.1
-
14
-
-
1842762647
-
A top-down, constraint-driven design methodology for analog integrated circuits
-
J. Huijsing, R. van der Plassche, and W. Sansen, Eds. Norwell, MA: Kluwer, ch. 13
-
E. Malavasi et al., “A top-down, constraint-driven design methodology for analog integrated circuits,” in Analog Circuit Design, J. Huijsing, R. van der Plassche, and W. Sansen, Eds. Norwell, MA: Kluwer, 1993, ch. 13, pp. 285-324.
-
(1993)
Analog Circuit Design
, pp. 285-324
-
-
Malavasi, E.1
-
16
-
-
0015107997
-
Computer analysis of nonlinear circuits, excluding radiation (CANCER)
-
L. Nagle and R. Rohrer, “Computer analysis of nonlinear circuits, excluding radiation (CANCER),” IEEE J. Solid-State Circuits, vol. SSC-6, pp. 166-182, Aug. 1971.
-
(1971)
IEEE J. Solid-State Circuits
, vol.SSC-6
, pp. 166-182
-
-
Nagle, L.1
Rohrer, R.2
-
19
-
-
0033719266
-
MOS transistor modeling for RF integrated circuit design
-
C. Enz, “MOS transistor modeling for RF integrated circuit design,” in Proc. IEEE Custom Integrated Circuit Conf (CICC), 2000, pp. 189-196.
-
(2000)
Proc. IEEE Custom Integrated Circuit Conf (CICC)
, pp. 189-196
-
-
Enz, C.1
-
20
-
-
0029757245
-
Multi-level and mixed-domain simulation of analog circuits and systems
-
yvol. 15, pp. 68-82, Jan. 1996.
-
(1996)
Y
, vol.15
, pp. 68-82
-
-
Saleh, R.1
Antao, B.2
Singh, J.3
-
21
-
-
0003824122
-
-
Norwell, MA: Kluwer
-
A. Vachoux, J.-M. Bergé, O. Levia, and J. Rouillard, Eds., Analog and Mixed-Signal Hardware Description Languages. Norwell, MA: Kluwer, 1997.
-
(1997)
Analog and Mixed-Signal Hardware Description Languages
-
-
Vachoux, A.1
Bergé, J.-M.2
Levia, O.3
Rouillard, J.4
-
23
-
-
0026204011
-
Consistency checking and optimization of macromodels
-
Y.-C. Ju, V. Rao, and R. Saleh, “Consistency checking and optimization of macromodels,” IEEE Trans. Computer-Aided Design, pp. 957-967, Aug. 1991.
-
(1991)
IEEE Trans. Computer-Aided Design
, pp. 957-967
-
-
Ju, Y.-C.1
Rao, V.2
Saleh, R.3
-
25
-
-
0029705516
-
Equation-based behavioral model generation for nonlinear analog circuits
-
C. Borchers, L. Hedrich, and E. Barke, “Equation-based behavioral model generation for nonlinear analog circuits,” in Proc. IEEE/ACM Design Automation Conf (DAC), 1996, pp. 236-239.
-
(1996)
Proc. IEEE/ACM Design Automation Conf (DAC)
, pp. 236-239
-
-
Borchers, C.1
Hedrich, L.2
Barke, E.3
-
26
-
-
0020826238
-
SWITCAP: A switched-capac-itor network analysis program-Part I: Basic features
-
S. Fang, Y. Tsividis, and O. Wing, “SWITCAP: A switched-capac-itor network analysis program-Part I: Basic features,” IEEE Circuits Syst. Mag., vol. 5, pp. 4-10, Sept. 1983.
-
(1983)
IEEE Circuits Syst. Mag
, vol.5
, pp. 4-10
-
-
Fang, S.1
Tsividis, Y.2
Wing, O.3
-
27
-
-
0020918080
-
SWITCAP: A switched-capac-itor network analysis program-Part I: Advanced applications
-
S. Fang, Y. Tsividis, and O. Wing, “SWITCAP: A switched-capac-itor network analysis program-Part I: Advanced applications,” IEEE Circuits Syst. Mag., vol. 5, pp. 41-46, Sept. 1983.
-
(1983)
IEEE Circuits Syst. Mag
, vol.5
, pp. 41-46
-
-
Fang, S.1
Tsividis, Y.2
Wing, O.3
-
28
-
-
0019547769
-
Time, frequency, and Z -domain modified nodal analysis of switched-capacitor networks
-
J. Vandewalle, H. De Man, and J. Rabaey, ‘Time, frequency, and Z -domain modified nodal analysis of switched-capacitor networks,” IEEE Trans. Circuits Syst., vol. CAS-28, pp. 186-195, Mar. 1981.
-
(1981)
IEEE Trans. Circuits Syst
, vol.CAS-28
, pp. 186-195
-
-
Vandewalle, J.1
De Man, H.2
Rabaey, J.3
-
29
-
-
0026369824
-
TOSCA: A user-friendly behavioral simulator for oversampling A/D converters
-
V. Dias, V. Liberali, and F. Maloberti, “TOSCA: A user-friendly behavioral simulator for oversampling A/D converters,” in Proc. IEEE Int. Symp. Circuits Syst. (ISCAS), 1991, pp. 2677-2680.
-
(1991)
Proc. IEEE Int. Symp. Circuits Syst. (ISCAS)
, pp. 2677-2680
-
-
Dias, V.1
Liberali, V.2
Maloberti, F.3
-
31
-
-
0029712768
-
Fast simulation algorithms for RF circuits
-
R. Telichevesky, K. Kundert, I. Elfadel, and J. White, “Fast simulation algorithms for RF circuits,” in Proc. IEEE Custom Integrated Circuits Conf (CICC), 1996, pp. 437-444.
-
(1996)
Proc. IEEE Custom Integrated Circuits Conf (CICC)
, pp. 437-444
-
-
Telichevesky, R.1
Kundert, K.2
Elfadel, I.3
White, J.4
-
32
-
-
0000190107
-
Introduction to RF simulation and its applications
-
K. Kundert, “Introduction to RF simulation and its applications,” IEEE J. Solid-State Circuits, vol. 34, pp. 1298-1319, Sept. 1999.
-
(1999)
IEEE J. Solid-State Circuits
, vol.34
, pp. 1298-1319
-
-
Kundert, K.1
-
33
-
-
0030408886
-
Computation of circuit waveform envelopes using an efficient, matrix-decomposed harmonic balance algorithm
-
P. Feldmann and J. Roychowdhury, “Computation of circuit waveform envelopes using an efficient, matrix-decomposed harmonic balance algorithm,” in Proc. IEEE/ACM Int. Conf Computer-Aided Design (ICCAD), 1996, pp. 295-300.
-
(1996)
Proc. IEEE/ACM Int. Conf Computer-Aided Design (ICCAD)
, pp. 295-300
-
-
Feldmann, P.1
Roychowdhury, J.2
-
34
-
-
0029487134
-
A high-level design and optimization tool for analog RF receiver front-ends
-
J. Crols, S. Donnay, M. Steyaert, and G. Gielen, “A high-level design and optimization tool for analog RF receiver front-ends,” in Proc. IEEE/ACM Int. Conf. Computer-Aided Design (ICCAD), 1995, pp. 550-553.
-
(1995)
Proc. IEEE/ACM Int. Conf. Computer-Aided Design (ICCAD)
, pp. 550-553
-
-
Crols, J.1
Donnay, S.2
Steyaert, M.3
Gielen, G.4
-
36
-
-
0033683216
-
Noise in mixers, oscillators, samplers, and logic: An introduction to cyclostationary noise
-
J. Phillips and K. Kundert, “Noise in mixers, oscillators, samplers, and logic: An introduction to cyclostationary noise,” in Proc. IEEE Custom Integrated Circuits Conf (CICC), 2000, pp. 431-439.
-
(2000)
Proc. IEEE Custom Integrated Circuits Conf (CICC)
, pp. 431-439
-
-
Phillips, J.1
Kundert, K.2
-
38
-
-
0025414182
-
Asymptotic waveform evaluation for timing analysis
-
L. Pillage and R. Rohrer, “Asymptotic waveform evaluation for timing analysis,” IEEE Trans. Computer-Aided Design, vol. 9, pp. 352-366, Apr. 1990.
-
(1990)
IEEE Trans. Computer-Aided Design
, vol.9
, pp. 352-366
-
-
Pillage, L.1
Rohrer, R.2
-
39
-
-
0030387972
-
A coordinate-transformed Arnoldi algorithm for generating guaranteed stable reduced-order models of RLC circuits
-
L. Silveira et al., “A coordinate-transformed Arnoldi algorithm for generating guaranteed stable reduced-order models of RLC circuits,” in Proc. IEEE/ACM Int. Conf Computer-Aided Design (ICCAD), 1996, pp. 288-294.
-
(1996)
Proc. IEEE/ACM Int. Conf Computer-Aided Design (ICCAD)
, pp. 288-294
-
-
Silveira, L.1
-
42
-
-
0030110592
-
Modeling and analysis of substrate coupling in integrated circuits
-
R. Gharpurey and R. Meyer, “Modeling and analysis of substrate coupling in integrated circuits,” IEEE J. Solid-State Circuits, vol. 31, pp. 344-353. Mar. 1996.
-
(1996)
IEEE J. Solid-State Circuits
, vol.31
, pp. 344-353
-
-
Gharpurey, R.1
Meyer, R.2
-
44
-
-
0011728654
-
Design techniques to reduce substrate noise
-
Huijsing, van de Plassche, and Sansen, Eds. Norwell, MA: Kluwer
-
T. Blalack. “Design techniques to reduce substrate noise,” in Advances in Analog Circuit Design, Huijsing, van de Plassche, and Sansen, Eds. Norwell, MA: Kluwer, 1999, pp. 193-217.
-
(1999)
Advances in Analog Circuit Design
, pp. 193-217
-
-
Blalack, T.1
-
45
-
-
0032668259
-
Efficient techniques for accurate modeling and simulation of substrate coupling in mixed-signal ICs
-
J. Costa, M. Chou, and L. Silveira, “Efficient techniques for accurate modeling and simulation of substrate coupling in mixed-signal ICs,” IEEE Trans. Computer-Aided Design, vol. 18, pp. 597-607, May 1999.
-
(1999)
IEEE Trans. Computer-Aided Design
, vol.18
, pp. 597-607
-
-
Costa, J.1
Chou, M.2
Silveira, L.3
-
46
-
-
0033078939
-
Substrate optimization based on semi-analytical techniques
-
E. Charbon, R. Gharpurey, R. Meyer, and A. Sangiovanni-Vincen-telli, “Substrate optimization based on semi-analytical techniques,” IEEE Trans. Computer-Aided Design, vol. 18, pp. 172-190, Feb. 1999.
-
(1999)
IEEE Trans. Computer-Aided Design
, vol.18
, pp. 172-190
-
-
Charbon, E.1
Gharpurey, R.2
Meyer, R.3
Sangiovanni-Vincen-Telli, A.4
-
47
-
-
0033700093
-
High-level simulation of substrate noise generation including power supply noise coupling
-
M. van Heijningen, M. Badaroglu, S. Donnay, M. Engels, and I. Bolsens, “High-level simulation of substrate noise generation including power supply noise coupling,” in Proc. IEEE/ACM Design Automation Conf (DAC), 2000, pp. 446-451.
-
(2000)
Proc. IEEE/ACM Design Automation Conf (DAC)
, pp. 446-451
-
-
Van Heijningen, M.1
Badaroglu, M.2
Donnay, S.3
Engels, M.4
Bolsens, I.5
-
48
-
-
0028374647
-
Symbolic analysis methods and applications for analog circuits: A tutorial overview
-
G. Gielen, R Wambacq, and W. Sansen, “Symbolic analysis methods and applications for analog circuits: A tutorial overview,” Proc. IEEE, vol. 82, pp. 287-304, Feb. 1994.
-
(1994)
Proc. IEEE
, vol.82
, pp. 287-304
-
-
Gielen, G.1
Wambacq, R.2
Sansen, W.3
-
49
-
-
0003788573
-
-
Piscataway, NJ: IEEE Press
-
F. Fernández, A. Rodríguez-Vazquez, J. Huertas, and G. Gielen, Symbolic Analysis Techniques-Applications to Analog Design Automation. Piscataway, NJ: IEEE Press, 1998.
-
(1998)
Symbolic Analysis Techniques-Applications to Analog Design Automation
-
-
Fernández, F.1
Rodríguez-Vazquez, A.2
Huertas, J.3
Gielen, G.4
-
50
-
-
0029264312
-
Efficient symbolic computation of approximated small-signal characteristics
-
P. Wambacq, F. Fernández, G. Gielen, W. Sansen, and A. Rodríguez-Vázquez, “Efficient symbolic computation of approximated small-signal characteristics,” IEEE J. Solid-State Circuits, vol. 30, pp. 327-330, Mar. 1995.
-
(1995)
IEEE J. Solid-State Circuits
, vol.30
, pp. 327-330
-
-
Wambacq, P.1
Fernández, F.2
Gielen, G.3
Sansen, W.4
Rodríguez-Vázquez, A.5
-
51
-
-
0024904709
-
ISAAC: A symbolic simulator for analog integrated circuits
-
G. Gielen, H. Walscharts, and W. Sansen, “ISAAC: A symbolic simulator for analog integrated circuits.” IEEE J. Solid-State Circuits. vol. 24, pp. 1587-1596, Dec. 1989.
-
(1989)
IEEE J. Solid-State Circuits
, vol.24
, pp. 1587-1596
-
-
Gielen, G.1
Walscharts, H.2
Sansen, W.3
-
52
-
-
0001638306
-
High-frequency distortion analysis of analog integrated circuits
-
P. Wambacq, G. Gielen, P. Kinget, and W. Sansen, “High-frequency distortion analysis of analog integrated circuits,” IEEE Trans. Circuits Syst. II, vol. 46, pp. 335-345, Mar. 1999.
-
(1999)
IEEE Trans. Circuits Syst. II
, vol.46
, pp. 335-345
-
-
Wambacq, P.1
Gielen, G.2
Kinget, P.3
Sansen, W.4
-
53
-
-
0024178682
-
A symbolic analysis tool for analog circuit design automation
-
S. Seda, M. Degrauwe, and W. Fichtner, “A symbolic analysis tool for analog circuit design automation,” in Proc. IEEE/ACM Int. Conf Computer-Aided Design (ICCAD), 1988, pp. 488-491.
-
(1988)
Proc. IEEE/ACM Int. Conf Computer-Aided Design (ICCAD)
, pp. 488-491
-
-
Seda, S.1
Degrauwe, M.2
Fichtner, W.3
-
54
-
-
0026251328
-
Interactive ac modeling and characterization of analog circuits via symbolic analysis
-
F. Fernández, A. Rodríguez-Vázquez, and J. Huertas, “Interactive ac modeling and characterization of analog circuits via symbolic analysis,” Kluwer Int. J. Analog Integrated Circuits Signal Processing, vol. 1, pp. 183-208, Nov. 1991.
-
(1991)
Kluwer Int. J. Analog Integrated Circuits Signal Processing
, vol.1
, pp. 183-208
-
-
Fernández, F.1
Rodríguez-Vázquez, A.2
Huertas, J.3
-
55
-
-
0030216744
-
A unified approach to the approximate symbolic analysis of large analog integrated circuits
-
Q. Yu and C. Sechen, “A unified approach to the approximate symbolic analysis of large analog integrated circuits,” IEEE Trans. Circuits Systems I, vol. 43, pp. 656-669, Aug. 1996.
-
(1996)
IEEE Trans. Circuits Systems I
, vol.43
, pp. 656-669
-
-
Yu, Q.1
Sechen, C.2
-
56
-
-
0032629529
-
Circuit complexity reduction for symbolic analysis of analog integrated circuits
-
W. Daems, G. Gielen, and W. Sansen, “Circuit complexity reduction for symbolic analysis of analog integrated circuits,” in Proc. IEEE/ACM Design Automation Conf, 1999, pp. 958-963.
-
(1999)
Proc. IEEE/ACM Design Automation Conf
, pp. 958-963
-
-
Daems, W.1
Gielen, G.2
Sansen, W.3
-
57
-
-
0028753180
-
DC small signal symbolic analysis of large analog integrated circuits
-
J. Hsu and C. Sechen, “DC small signal symbolic analysis of large analog integrated circuits,” IEEE Trans. Circuits Systems, vol. 41, pp. 817-828, Dec. 1994.
-
(1994)
IEEE Trans. Circuits Systems
, vol.41
, pp. 817-828
-
-
Hsu, J.1
Sechen, C.2
-
58
-
-
0022688734
-
Flowgraph analysis of large electronic networks
-
J. Starzyk and A. Konczykowska, “Flowgraph analysis of large electronic networks,” IEEE Trans. Circuits Syst., vol. CAS-33, pp. 302-315, Mar. 1986.
-
(1986)
IEEE Trans. Circuits Syst
, vol.CAS-33
, pp. 302-315
-
-
Starzyk, J.1
Konczykowska, A.2
-
59
-
-
1942437146
-
A hierarchical approach for the symbolic analysis of large analog integrated circuits
-
O. Guerra, E. Roca, F. Fernández, and A. Rodríguez-Vázquez, “A hierarchical approach for the symbolic analysis of large analog integrated circuits,” in Proc. IEEE Design Automation and Test in Europe Conf (DATE), 2000, pp. 48-52.
-
(2000)
Proc. IEEE Design Automation and Test in Europe Conf (DATE)
, pp. 48-52
-
-
Guerra, O.1
Roca, E.2
Fernández, F.3
Rodríguez-Vázquez, A.4
-
60
-
-
0033882369
-
Canonical symbolic analysis of large analog circuits with determinant decision diagrams
-
C.-J. Shi and X.-D. Tan, “Canonical symbolic analysis of large analog circuits with determinant decision diagrams,” IEEE Trans. Computer-Aided Design, vol. 19, pp. 1-18, Jan. 2000.
-
(2000)
IEEE Trans. Computer-Aided Design
, vol.19
, pp. 1-18
-
-
Shi, C.-J.1
Tan, X.-D.2
-
61
-
-
0003119486
-
Hierarchical symbolic analysis of analog integrated circuits via determinant decision diagrams
-
X.-D. Tan and C.-J. Shi, “Hierarchical symbolic analysis of analog integrated circuits via determinant decision diagrams,” IEEE Trans. Computer-Aided Design, vol. 19, pp. 401-412, April 2000.
-
(2000)
IEEE Trans. Computer-Aided Design
, vol.19
, pp. 401-412
-
-
Tan, X.-D.1
Shi, C.-J.2
-
62
-
-
0024682099
-
BLADES: An artificial intelligence approach to analog circuit design
-
F. El-Turky and E. Perry, “BLADES: An artificial intelligence approach to analog circuit design,” IEEE Trans. Computer-Aided Design, vol. 8, pp. 680-691, June 1989.
-
(1989)
IEEE Trans. Computer-Aided Design
, vol.8
, pp. 680-691
-
-
El-Turky, F.1
Perry, E.2
-
64
-
-
85013436417
-
-
P. Veselinovic et al “A flexible topology selection program as part of an analog synthesis system," in Proc. IEEE Eur. Design Test Conf. (ED&TC) 1995, pp. 119-123.
-
(1995)
, pp. 119-123
-
-
Veselinovic, P.1
-
66
-
-
0029287787
-
Simultaneous topology selection and sizing of cell-level analog circuits
-
P. Maulik, L. R. Carley, and R. Rutenbar, “Simultaneous topology selection and sizing of cell-level analog circuits,” IEEE Trans. Computer-Aided Design, vol. 14, pp. 401-412, Apr. 1995.
-
(1995)
IEEE Trans. Computer-Aided Design
, vol.14
, pp. 401-412
-
-
Maulik, P.1
Carley, L.R.2
Rutenbar, R.3
-
67
-
-
0026405818
-
SEAS: A simulated evolution approach for analog circuit synthesis
-
Z. Ning et al., “SEAS: A simulated evolution approach for analog circuit synthesis,” in Proc. IEEE Custom Integrated Circuits Conf (CICC), 1991, pp. 5.2.1-5.2.4.
-
(1991)
Proc. IEEE Custom Integrated Circuits Conf (CICC)
, pp. 1-5
-
-
Ning, Z.1
-
70
-
-
84936071801
-
IDAC: An interactive design tool for analog CMOS circuits
-
M. Degrauwe et al., “IDAC: An interactive design tool for analog CMOS circuits,” IEEE J. Solid-State Circuits, vol. 22, pp. 1106-1115, Dec. 1987.
-
(1987)
IEEE J. Solid-State Circuits
, vol.22
, pp. 1106-1115
-
-
Degrauwe, M.1
-
71
-
-
22944443134
-
Analog CAD for consumer ICs
-
J. Huijsing, R. van der Plassche, and W. Sansen. Eds. Norwell, MA: Kluwer
-
G. Beenker, J. Conway, G. Schrooten, and A. Slenter, “Analog CAD for consumer ICs,” in Analog Circuit Design, J. Huijsing, R. van der Plassche, and W. Sansen. Eds. Norwell, MA: Kluwer, 1993, pp. 347-367.
-
(1993)
Analog Circuit Design
, pp. 347-367
-
-
Beenker, G.1
Conway, J.2
Schrooten, G.3
Slenter, A.4
-
72
-
-
0042192171
-
A spreadsheet interface for analog design knowledge capture and reuse
-
R. Henderson et al., “A spreadsheet interface for analog design knowledge capture and reuse,” in Proc. IEEE Custom Integrated Circuits Conf. (CICC), 1993, pp. 13.3.1-13.3.4.
-
(1993)
Proc. IEEE Custom Integrated Circuits Conf. (CICC)
, pp. 13.3.1-13.3.4
-
-
Henderson, R.1
-
73
-
-
33646925565
-
Automated high level synthesis of data conversion systems
-
Soin, Maloberti. and Franca, Eds. Stevenage, U. K.: Peregrinus
-
N. Horta, J. Franca, and C. Leme, “Automated high level synthesis of data conversion systems,” in Analogue-Digital ASICs-Circuit Techniques, Design Tools and Applications, Soin, Maloberti. and Franca, Eds. Stevenage, U. K.: Peregrinus. 1991.
-
(1991)
Analogue-Digital Asics-Circuit Techniques, Design Tools and Applications
-
-
Horta, N.1
Franca, J.2
Leme, C.3
-
74
-
-
33747784418
-
Synthesis of high-speed A/D converter architectures with flexible functional simulation capabilities
-
J. Vital and J. Franca, “Synthesis of high-speed A/D converter architectures with flexible functional simulation capabilities.” in Proc. IEEE Int. Symp. Circuits Syst. (ISCAS), 1992, pp. 2156-2159.
-
(1992)
Proc. IEEE Int. Symp. Circuits Syst. (ISCAS)
, pp. 2156-2159
-
-
Vital, J.1
Franca, J.2
-
75
-
-
0029255630
-
Analog IC design automation-I: Automated circuit generation: New concepts and methods
-
C. Toumazou and C. Makris, “Analog IC design automation-I: Automated circuit generation: New concepts and methods,” IEEE Trans. Computer-Aided Design, vol. 14, pp. 218-238, Feb. 1995.
-
(1995)
IEEE Trans. Computer-Aided Design
, vol.14
, pp. 218-238
-
-
Toumazou, C.1
Makris, C.2
-
76
-
-
0029250875
-
Analog IC design automation-II: Automated circuit correction by qualitative reasoning
-
C. Makris and C. Toumazou, “Analog IC design automation-II: Automated circuit correction by qualitative reasoning,” IEEE Trans. Computer-Aided Design, vol. 14, pp. 239-254, Feb. 1995.
-
(1995)
IEEE Trans. Computer-Aided Design
, vol.14
, pp. 239-254
-
-
Makris, C.1
Toumazou, C.2
-
77
-
-
0023965771
-
A knowledge-based approach to analog IC design
-
Feb
-
B. Sheu, A. Fung, and Y.-N. Lai, “A knowledge-based approach to analog IC design,” IEEE Trans. Circuits Syst., vol. 35, pp. 256-258, Feb. 1988.
-
(1988)
IEEE Trans. Circuits Syst
, vol.35
, pp. 256-258
-
-
Sheu, B.1
Fung, A.2
Lai, Y.-N.3
-
78
-
-
0026946787
-
STAIC: An interactive framework for synthesizing CMOS and BiCMOS analog circuits
-
J. Harvey, M. Elmasry and B. Leung, “STAIC: An interactive framework for synthesizing CMOS and BiCMOS analog circuits,” IEEE Trans. Computer-Aided Design, vol. 11, pp. 1402-1416, Nov. 1992.
-
(1992)
IEEE Trans. Computer-Aided Design
, vol.11
, pp. 1402-1416
-
-
Harvey, J.1
Elmasry, M.2
Leung, B.3
-
79
-
-
0025448791
-
Analog circuit design optimization based on symbolic simulation and simulated annealing
-
G. Gielen, H. Walscharts, and W. Sansen, “Analog circuit design optimization based on symbolic simulation and simulated annealing,” IEEE J. Solid-State Circuits, vol. 25, pp. 707-713, June 1990.
-
(1990)
IEEE J. Solid-State Circuits
, vol.25
, pp. 707-713
-
-
Gielen, G.1
Walscharts, H.2
Sansen, W.3
-
80
-
-
0027045462
-
DONALD: A workbench or interactive design space exploration and sizing of analog circuits
-
K. Swings and W. Sansen, “DONALD: A workbench or interactive design space exploration and sizing of analog circuits,” in Proc. IEEE Eur. Design Automation Conf (EDAC). 1991, pp. 475-479.
-
(1991)
Proc. IEEE Eur. Design Automation Conf (EDAC)
, pp. 475-479
-
-
Swings, K.1
Sansen, W.2
-
82
-
-
0029342926
-
An analog module generator for mixed analog/digital ASIC design
-
July-Aug
-
G. Gielen et al., “An analog module generator for mixed analog/digital ASIC design,” Wiley Int. J. Circuit Theory Applicai, vol. 23, pp. 269-283, July-Aug. 1995.
-
(1995)
Wiley Int. J. Circuit Theory Applicai
, vol.23
, pp. 269-283
-
-
Gielen, G.1
-
83
-
-
0029341997
-
A vertically-integrated tool for automated design of 3ZA modulators
-
F. Medeiro, B. Pérez-Verdu, A. Rodriguez-Vazquez, and J. Huertas, “A vertically-integrated tool for automated design of 3ZA modulators,” IEEE J. Solid-State Circuits, vol. 30, pp. 762-772, July 1995.
-
(1995)
IEEE J. Solid-State Circuits
, vol.30
, pp. 762-772
-
-
Medeiro, F.1
Pérez-Verdu, B.2
Rodriguez-Vazquez, A.3
Huertas, J.4
-
84
-
-
0032667151
-
Behavioral synthesis of analog systems using two-layered design space exploration
-
A. Doboli, A. Nunez-Aldana, N. Dhanwada, S. Ganesan, and R. Ve-muri, “Behavioral synthesis of analog systems using two-layered design space exploration,” in Proc. ACM/IEEE Design Automation Conf. (DAC), 1999, pp. 951-957.
-
(1999)
Proc. ACM/IEEE Design Automation Conf. (DAC)
, pp. 951-957
-
-
Doboli, A.1
Nunez-Aldana, A.2
Dhanwada, N.3
Ganesan, S.4
Ve-Muri, R.5
-
85
-
-
0032307687
-
An efficient dc root solving algorithm with guaranteed convergence for analog integrated CMOS circuits
-
F. Leyn, G. Gielen, and W. Sansen, “An efficient dc root solving algorithm with guaranteed convergence for analog integrated CMOS circuits,” in Proc. IEEE/ACM Int. Conf Computer-Aided Design (ICCAD), 1998, pp. 304-307.
-
(1998)
Proc. IEEE/ACM Int. Conf Computer-Aided Design (ICCAD)
, pp. 304-307
-
-
Leyn, F.1
Gielen, G.2
Sansen, W.3
-
86
-
-
0032312684
-
GPCAD: A tool for CMOS op-amp synthesis
-
M. Hershenson, S. Boyd, and T. Lee, “GPCAD: A tool for CMOS op-amp synthesis,” in Proc. IEEE/ACM hit. Conf. Computer-Aided Design (ICCAD), 1998, pp. 296-303.
-
(1998)
Proc. IEEE/ACM Hit. Conf. Computer-Aided Design (ICCAD)
, pp. 296-303
-
-
Hershenson, M.1
Boyd, S.2
Lee, T.3
-
87
-
-
0032683657
-
“Optimization of inductor circuits via geometric programming
-
JM. Hershenson, S. Mohan, S. Boyd, and T. Lee, “Optimization of inductor circuits via geometric programming,’ in Proc. IEEE/ACM Design Automation Conf. (DAC), 1999. pp. 994-998.
-
(1999)
Proc. IEEE/ACM Design Automation Conf. (DAC)
, pp. 994-998
-
-
Hershenson, J.M.1
Mohan, S.2
Boyd, S.3
Lee, T.4
-
88
-
-
0001391562
-
Automated network design-The frequency domain case
-
Aug
-
S. Director and R. Rohrer, “Automated network design-The frequency domain case." IEEE Trans, Circuit Theory, vol. 16, pp. 330-337, Aug. 1969.
-
(1969)
IEEE Trans, Circuit Theory
, vol.16
, pp. 330-337
-
-
Director, S.1
Rohrer, R.2
-
89
-
-
0023994941
-
DE-LIGHT.SPICE: An optimization-based system for the design of integrated circuits
-
W. Nye, D. Riley, A. Sangiovanni-Vincentelli, and A. Tits, “DE-LIGHT.SPICE: An optimization-based system for the design of integrated circuits,” IEEE Trans. Computer-Aided Design. vol. 7, pp. 501-518, Apr. 1988.
-
(1988)
IEEE Trans. Computer-Aided Design
, vol.7
, pp. 501-518
-
-
Nye, W.1
Riley, D.2
Sangiovanni-Vincentelli, A.3
Tits, A.4
-
90
-
-
0028699239
-
A statistical optimization-based approach for automated sizing of analog cells
-
F. Medeiro et al, “A statistical optimization-based approach for automated sizing of analog cells.” in Proc. ACM/IEEE Int. Conf Computer-Aided Design (ICCAD), 1994, pp. 594-597.
-
(1994)
Proc. ACM/IEEE Int. Conf Computer-Aided Design (ICCAD)
, pp. 594-597
-
-
Medeiro, F.1
-
91
-
-
0030107342
-
Synthesis of high-performance analog circuits in ASTRX/OBLX
-
E. Ochotta, R. Rutenbar, and L. R. Carley, “Synthesis of high-performance analog circuits in ASTRX/OBLX,” IEEE Trans. Computer-Aided Design, vol. 15, pp. 273-294, Mar. 1996.
-
(1996)
IEEE Trans. Computer-Aided Design
, vol.15
, pp. 273-294
-
-
Ochotta, E.1
Rutenbar, R.2
Carley, L.R.3
-
92
-
-
0004106930
-
-
Norwell, MA: Kluwer
-
E. Ochotta, T. Mukherjee, R. Rutenbar, and L. R. Carley. Practical Synthesis of High-Performance Analog Circuits. Norwell, MA: Kluwer, 1998.
-
(1998)
Practical Synthesis of High-Performance Analog Circuits
-
-
Ochotta, E.1
Mukherjee, T.2
Rutenbar, R.3
Carley, L.R.4
-
93
-
-
33845438821
-
The generalized boundary curve-A common method for automatic nominal design and design centering of analog circuits
-
R. Schwencker, F. Schenkel, H. Graeb, and K. Antreich, “The generalized boundary curve-A common method for automatic nominal design and design centering of analog circuits,” in Proc. IEEE Design Automation and Test in Europe Conf. (DATE), 2000, pp. 42-47.
-
(2000)
Proc. IEEE Design Automation and Test in Europe Conf. (DATE)
, pp. 42-47
-
-
Schwencker, R.1
Schenkel, F.2
Graeb, H.3
Antreich, K.4
-
94
-
-
0032597727
-
ANACONDA: Robust synthesis of analog circuits via stochastic pattern search
-
R. Phelps, M. Krasnicki, R. Rutenbar, L. R. Carley, and J. Heliums, “ANACONDA: Robust synthesis of analog circuits via stochastic pattern search,” in Pwc. Custom Integrated Circuits Conf (CICC), 1999, pp. 567-570.
-
(1999)
Pwc. Custom Integrated Circuits Conf (CICC)
, pp. 567-570
-
-
Phelps, R.1
Krasnicki, M.2
Rutenbar, R.3
Carley, L.R.4
Heliums, J.5
-
95
-
-
0032639484
-
MAELSTROM: Efficient simulation-based synthesis for custom analog cells
-
M. Krasnicki, R. Phelps, R. Rutenbar, and L. R. Carley, “MAELSTROM: Efficient simulation-based synthesis for custom analog cells,” in Proc. ACM/IEEE Design Automation Conf (DAC), 1999, pp. 945-950.
-
(1999)
Proc. ACM/IEEE Design Automation Conf (DAC)
, pp. 945-950
-
-
Krasnicki, M.1
Phelps, R.2
Rutenbar, R.3
Carley, L.R.4
-
96
-
-
0033712180
-
A case study of synthesis for industrial-scale analog IP: Redesign of the equalizer/filter frontend for an ADSL CODEC
-
R. Phelps, M. Krasnicki, R. Rutenbar, L. R. Carley, and J. Heliums, “A case study of synthesis for industrial-scale analog IP: Redesign of the equalizer/filter frontend for an ADSL CODEC,” in Prvc. ACM/IEEE Design Automation Conf (DAC), 2000, pp. 1-6.
-
(2000)
Prvc. ACM/IEEE Design Automation Conf (DAC)
, pp. 1-6
-
-
Phelps, R.1
Krasnicki, M.2
Rutenbar, R.3
Carley, L.R.4
Heliums, J.5
-
97
-
-
0025414530
-
Operational-amplifier compilation with performance optimization
-
H. Onodera, H. Kanbara, and K. Tamaru, “Operational-amplifier compilation with performance optimization,” IEEE J. Solid-State Circuits. vol. 25, pp. 466-473, Apr. 1990.
-
(1990)
IEEE J. Solid-State Circuits
, vol.25
, pp. 466-473
-
-
Onodera, H.1
Kanbara, H.2
Tamaru, K.3
-
98
-
-
0029487134
-
A high-level design and optimization tool for analog RF receiver front-ends
-
J. Crols, S. Donnay, M. Steyaert, and G. Gielen, “A high-level design and optimization tool for analog RF receiver front-ends,” in Pwc. Int. Conf Computer-Aided Design (ICCAD), Nov. 1995, pp. 550-553.
-
(1995)
Pwc. Int. Conf Computer-Aided Design (ICCAD)
, pp. 550-553
-
-
Crols, J.1
Donnay, S.2
Steyaert, M.3
Gielen, G.4
-
99
-
-
0005387493
-
A switched-capacitor filter silicon compiler
-
J. Assael, P. Senn and M. Tawfik, “A switched-capacitor filter silicon compiler,” IEEE J. Solid-State Circuits, vol. 23, pp. 166-174, Feb. 1988.
-
(1988)
IEEE J. Solid-State Circuits
, vol.23
, pp. 166-174
-
-
Assael, J.1
Senn, P.2
Tawfik, M.3
-
100
-
-
0030084385
-
CAD tools for data converter design: An overview
-
Feb
-
G. Gielen and J. Franca, “CAD tools for data converter design: An overview,” IEEE Trans. Circuits Systems II:, vol. 43, pp. 77-89, Feb.1996.
-
(1996)
IEEE Trans. Circuits Systems II
, vol.43
, pp. 77-89
-
-
Gielen, G.1
Franca, J.2
-
104
-
-
0032319738
-
Efficient analog circuit synthesis with simultaneous yield and robustness optimization
-
Nov
-
G. Debyser and G. Gielen, “Efficient analog circuit synthesis with simultaneous yield and robustness optimization,” in Proc. IEEE/ACM Int. Conf Computer-Aided Design (ICCAD). Nov. 1998, pp. 308-311.
-
(1998)
Proc. IEEE/ACM Int. Conf Computer-Aided Design (ICCAD
, pp. 308-311
-
-
Debyser, G.1
Gielen, G.2
-
105
-
-
0003212510
-
Analog module generators for silicon compilation
-
J. Kuhn, “Analog module generators for silicon compilation,” in VLSI System Design. 1987.
-
(1987)
VLSI System Design
-
-
Kuhn, J.1
-
106
-
-
0024647840
-
ILAC: An automated layout tool for analog CMOS circuits
-
J. Rijmenants et al., “ILAC: An automated layout tool for analog CMOS circuits,” IEEE J. Solid-State Circuits, vol. 24, pp. 417-425, Apr. 1989.
-
(1989)
IEEE J. Solid-State Circuits
, vol.24
, pp. 417-425
-
-
Rijmenants, J.1
-
107
-
-
0003591549
-
-
Norwell, MA: Kluwer
-
J. Cohn, D. Garrod, R. Rutenbar and L. R. Carley, Analog DeviceLevel Layout Generation. Norwell, MA: Kluwer, 1994.
-
(1994)
Analog Devicelevel Layout Generation
-
-
Cohn, J.1
Garrod, D.2
Rutenbar, R.3
Carley, L.R.4
-
109
-
-
0026118974
-
KOAN/ANA-GRAM II: New tools for device-level analog placement and routing
-
J. Cohn, D. Garrod, R. Rutenbar, and L. R. Carley. “KOAN/ANA-GRAM II: New tools for device-level analog placement and routing,” IEEE J. Solid-State Circuits. vol. 26, pp. 330-342, Mar. 1991.
-
(1991)
IEEE J. Solid-State Circuits
, vol.26
, pp. 330-342
-
-
Cohn, J.1
Garrod, D.2
Rutenbar, R.3
Carley, L.R.4
-
111
-
-
0027559437
-
ALSYN: Flexible rule-based layout synthesis for analog ICs
-
V. Meyer zu Bexten, C. Moraga, R. Klinke, W. Brockherde, and K. Hess, “ALSYN: Flexible rule-based layout synthesis for analog ICs,” IEEE J. Solid-State Circuits. vol. 28. pp. 261-268, Mar. 1993.
-
(1993)
IEEE J. Solid-State Circuits
, vol.28
, pp. 261-268
-
-
Meyer Zu Bexten, V.1
Moraga, C.2
Klinke, R.3
Brockherde, W.4
Hess, K.5
-
112
-
-
0030214354
-
Automation of IC layout with analog constraints
-
E. Malavasi, E. Charbon, E. Felt, and A. Sangiovanni-Vincentelli, “Automation of IC layout with analog constraints.” IEEE Trans. Computer-Aided Design, vol. 15. pp. 923-942, Aug. 1996.
-
(1996)
IEEE Trans. Computer-Aided Design
, vol.15
, pp. 923-942
-
-
Malavasi, E.1
Charbon, E.2
Felt, E.3
Sangiovanni-Vincentelli, A.4
-
114
-
-
22944453887
-
A constraint-driven placement methodology for analog integrated circuits
-
May
-
E. Charbon, E. Malavasi, U. Choudhury, A. Casotto, and A. Sangio-vanni-Vincentelli, “A constraint-driven placement methodology for analog integrated circuits; in Proc. IEEE Custom Integrated Circuits Conf. (CICC). May 1992, pp. 28.2.1-28.2.4.
-
(1992)
Proc. IEEE Custom Integrated Circuits Conf. (CICC)
, pp. 1-28
-
-
Charbon, E.1
Malavasi, E.2
Choudhury, U.3
Casotto, A.4
Sangio-Vanni-Vincentelli, A.5
-
115
-
-
0029344797
-
Symbolic compaction with analog constraints
-
July-Aug
-
E. Malavasi, E. Felt, E. Charbon, and A. Sangiovanni-Vincentelli, “Symbolic compaction with analog constraints,” Wiley Int. Journal Circuit Theory Applicat. vol. 23, pp. 433-452, July-Aug. 1995.
-
(1995)
Wiley Int. Journal Circuit Theory Applicat
, vol.23
, pp. 433-452
-
-
Malavasi, E.1
Felt, E.2
Charbon, E.3
Sangiovanni-Vincentelli, A.4
-
117
-
-
0029345604
-
A performance-driven placement tool for analog integrated circuits
-
K. Lampaert, G. Gielen, and W. Sansen, “A performance-driven placement tool for analog integrated circuits,” IEEE J. Solid-State Circuits, vol. 30, pp. 773-780, July 1995.
-
(1995)
IEEE J. Solid-State Circuits
, vol.30
, pp. 773-780
-
-
Lampaert, K.1
Gielen, G.2
Sansen, W.3
-
119
-
-
0027539610
-
Automatic generation of parasitic constraints for performance-constrained physical design of analog circuits
-
U. Choudhury and A. Sangiovanni-Vincentelli, “Automatic generation of parasitic constraints for performance-constrained physical design of analog circuits,” IEEE Trans. Computer-Aided Design. vol. 12, pp. 208-224, Feb. 1993.
-
(1993)
IEEE Trans. Computer-Aided Design
, vol.12
, pp. 208-224
-
-
Choudhury, U.1
Sangiovanni-Vincentelli, A.2
-
121
-
-
0029220994
-
Optimum CMOS stack generation with analog constraints
-
E. Malavasi and D. Pandini, “Optimum CMOS stack generation with analog constraints,” IEEE Trans. Computer-Aided Design, vol. 14. pp. 107-122, Jan. 1995.
-
(1995)
IEEE Trans. Computer-Aided Design
, vol.14
, pp. 107-122
-
-
Malavasi, E.1
Pandini, D.2
-
123
-
-
85029646146
-
A performance-driven placement algorithm with simultaneous place&route optimization for analog IC's
-
J. Prieto, A. Rueda, J. Quintana, and J. Huertas, “A performance-driven placement algorithm with simultaneous place&route optimization for analog IC's,” in Proc. IEEE Eur. Design Test Conf. (ED&TC), 1997, pp. 389-394.
-
(1997)
Proc. IEEE Eur. Design Test Conf. (Ed&Tc)
, pp. 389-394
-
-
Prieto, J.1
Rueda, A.2
Quintana, J.3
Huertas, J.4
-
124
-
-
0024902637
-
An efficient algorithm for layout compaction problem with symmetry constraints
-
Nov
-
R. Okuda, T. Sato, H. Onodera, and K. Tamuru, “An efficient algorithm for layout compaction problem with symmetry constraints,” in Proc. ACM/IEEE Int. Conf Computer-Aided Design (ICCAD), Nov. 1989, pp. 148-151.
-
(1989)
Proc. ACM/IEEE Int. Conf Computer-Aided Design (ICCAD)
, pp. 148-151
-
-
Okuda, R.1
Sato, T.2
Onodera, H.3
Tamuru, K.4
-
125
-
-
0027073999
-
Techniques for simultaneous placement and routing of custom analog cells in KOAN/ANAGRAM II
-
J. Cohn, D. Garrod, R. Rutenbar, and L. R. Carley. “Techniques for simultaneous placement and routing of custom analog cells in KOAN/ANAGRAM II.” in Proc. ACM/IEEE Int. Conf Computer-Aided Design (ICCAD), Nov. 1991, pp. 394-397.
-
(1991)
Proc. ACM/IEEE Int. Conf Computer-Aided Design (ICCAD)
, pp. 394-397
-
-
Cohn, J.1
Garrod, D.2
Rutenbar, R.3
Carley, L.R.4
-
126
-
-
0023030156
-
A methodology for automated layout of switched-capacitor filters
-
Nov
-
H. Yaghutiel, A. Sangiovanni-Vincentelli, and P. Gray, “A methodology for automated layout of switched-capacitor filters,” in Pme. ACM/IEEE Int. Conf Computer-Aided Design (ICCAD), Nov. 1986, pp. 444-447.
-
(1986)
Pme. ACM/IEEE Int. Conf Computer-Aided Design (ICCAD)
, pp. 444-447
-
-
Yaghutiel, H.1
Sangiovanni-Vincentelli, A.2
Gray, P.3
-
128
-
-
0024646662
-
A generalized approach to routing mixed analog and digital signal nets in a channel
-
R. Gyurcsik and J. Jeen. “A generalized approach to routing mixed analog and digital signal nets in a channel,” IEEE J. Solid-State Circuits, vol. 24, pp. 436-442, Apr. 1989.
-
(1989)
IEEE J. Solid-State Circuits
, vol.24
, pp. 436-442
-
-
Gyurcsik, R.1
Jeen, J.2
-
129
-
-
0027576850
-
Constraint-based channel routing for analog and mixed analog/digital circuits
-
U. Choudhury and A. Sangiovanni-Vincentelli, “Constraint-based channel routing for analog and mixed analog/digital circuits.” IEEE Trans. Computer-Aided Design, vol. 12. pp. 497-510, Apr. 1993.
-
(1993)
IEEE Trans. Computer-Aided Design
, vol.12
, pp. 497-510
-
-
Choudhury, U.1
Sangiovanni-Vincentelli, A.2
-
130
-
-
0026966663
-
System-level routing of mixed-signal ASICs in WREN
-
S. Mitra, S. Nag, R. Rutenbar, and L. R. Carley, “System-level routing of mixed-signal ASICs in WREN,” in ACM/IEEE Int. Conf. Computer-Aided Design (ICCAD), Nov. 1992.
-
(1992)
ACM/IEEE Int. Conf. Computer-Aided Design (ICCAD)
-
-
Mitra, S.1
Nag, S.2
Rutenbar, R.3
Carley, L.R.4
-
131
-
-
0029270756
-
Substrate-aware mixed-signal macrocell placement in WRIGHT
-
S. Mitra, R. Rutenbar, L. R. Caney, and D. Allstot. “Substrate-aware mixed-signal macrocell placement in WRIGHT.” IEEE J. Solid-State Circuits, vol. 30. pp. 269-278, Mar. 1995.
-
(1995)
IEEE J. Solid-State Circuits
, vol.30
, pp. 269-278
-
-
Mitra, S.1
Rutenbar, R.2
Caney, L.R.3
Allstot, D.4
-
132
-
-
0028384192
-
Addressing substrate coupling in mixed-mode ICs: Simulation and power distribution synthesis
-
B. Stanisic, N. Verghese, R. Rutenbar, L. R. Carley, and D. Allstot. “Addressing substrate coupling in mixed-mode ICs: Simulation and power distribution synthesis,” IEEE J. Solid-State Circuits, vol. 29. Mar. 1994.
-
(1994)
IEEE J. Solid-State Circuits
, vol.29
-
-
Stanisic, B.1
Verghese, N.2
Rutenbar, R.3
Carley, L.R.4
Allstot, D.5
-
135
-
-
0028256775
-
Circuit analysis and optimization driven by worst-case distances
-
K. Antreich, H. Graeb, and C. Wieser, “Circuit analysis and optimization driven by worst-case distances,” IEEE Trans. Computer-Aided Design, vol. 13, pp. 57-71, Jan. 1994.
-
(1994)
IEEE Trans. Computer-Aided Design
, vol.13
, pp. 57-71
-
-
Antreich, K.1
Graeb, H.2
Wieser, C.3
-
136
-
-
0027625646
-
Yield optimization of analog ICs using two-step analytic modeling methods,”
-
C. Guardiani, P. Scandolara, J. Benkoski, and G. Nicollini, “Yield optimization of analog IC’s using two-step analytic modeling methods,” IEEE J. Solid-State Circuits, vol. 28, pp. 778-783, July 1993.
-
(1993)
IEEE J. Solid-State Circuits
, vol.28
, pp. 778-783
-
-
Guardiani, C.1
Scandolara, P.2
Benkoski, J.3
Nicollini, G.4
-
137
-
-
0032641398
-
Parametric yield formulation of MOS ICs affected by mismatch effect,”
-
M. Conti, P. Crippa, S. Orcioni, and C. Turchetti, “Parametric yield formulation of MOS IC’s affected by mismatch effect,” IEEE Trans. Computer-Aided Design, vol. 18, pp. 582-596, May 1999.
-
(1999)
IEEE Trans. Computer-Aided Design
, vol.18
, pp. 582-596
-
-
Conti, M.1
Crippa, P.2
Orcioni, S.3
Turchetti, C.4
-
138
-
-
0001900396
-
Test and design for testability of analog and mixed-signal integrated circuits
-
H. Dedieu, Ed. Amsterdam, The Netherlands: Elsevier
-
J. Huertas, “Test and design for testability of analog and mixed-signal integrated circuits,” in Selected Topics in Circuits and Systems, H. Dedieu, Ed. Amsterdam, The Netherlands: Elsevier, 1993, pp. 77-156.
-
(1993)
Selected Topics in Circuits and Systems
, pp. 77-156
-
-
Huertas, J.1
-
141
-
-
0012426533
-
Automatic fault extraction and simulation of layout realistic faults for integrated analogue circuits
-
C. Sebeke, J. Teixeira, and M. Ohletz, “Automatic fault extraction and simulation of layout realistic faults for integrated analogue circuits,” in Proc. IEEE Eur. Design Test Conf (ED&TC), 1995, pp. 464-468.
-
(1995)
Proc. IEEE Eur. Design Test Conf (Ed&Tc)
, pp. 464-468
-
-
Sebeke, C.1
Teixeira, J.2
Ohletz, M.3
-
143
-
-
0030709160
-
Automated test pattern generation for analog integrated circuits
-
W. Verhaegen, G. Van der Plas, and G. Gielen, “Automated test pattern generation for analog integrated circuits,” in Proc. IEEE VLSI TestSymp. (VTS), 1997, pp. 296-301.
-
(1997)
Proc. IEEE VLSI Testsymp. (VTS)
, pp. 296-301
-
-
Verhaegen, W.1
Van Der Plas, G.2
Gielen, G.3
-
144
-
-
0024124547
-
Design for testability of mixed signal integrated circuits
-
K. Wagner and T. Williams, “Design for testability of mixed signal integrated circuits,” in Proc. IEEE Int. Test Conf (ITC), 1988, pp. 823-829.
-
(1988)
Proc. IEEE Int. Test Conf (ITC)
, pp. 823-829
-
-
Wagner, K.1
Williams, T.2
-
145
-
-
0025448207
-
Built-in self-test (BIST) structure for analog circuit fault diagnosis
-
June
-
C. Wey, “Built-in self-test (BIST) structure for analog circuit fault diagnosis,” IEEE Trans. Instrum. Meas., vol. 39, pp. 517-521, June 1990.
-
(1990)
IEEE Trans. Instrum. Meas
, vol.39
, pp. 517-521
-
-
Wey, C.1
-
146
-
-
0029721649
-
Oscillation-test strategy for analog and mixed-signal integrated circuits
-
K. Arabi and B. Kaminska, “Oscillation-test strategy for analog and mixed-signal integrated circuits,” in Proc. IEEE VLSI Test Symp. (VTS), 1996, pp. 476-482.
-
(1996)
Proc. IEEE VLSI Test Symp. (VTS)
, pp. 476-482
-
-
Arabi, K.1
Kaminska, B.2
-
148
-
-
0002155708
-
Ohletz, “Hybrid built-in self test (HBIST) for mixed analogue/digital integrated circuits,” in
-
M
-
M. Ohletz, “Hybrid built-in self test (HBIST) for mixed analogue/digital integrated circuits,” in Proc. IEEE Eur. Test Conf (ETC), 1991, pp. 307-316.
-
(1991)
Proc. IEEE Eur. Test Conf (ETC)
, pp. 307-316
-
-
|