A performance-driven placement algorithm with simultaneous place&route optimization for analog IC's

Proceedings of the 1997 European Conference on Design and Test, EDTC 1997

Volumn , Issue , 1997, Pages 389-394

  Prieto, Juan A ^a   Rueda, Adoración ^a   Quintana, José M ^a   Huertas, Jose L ^a  

^a INSTITUTO DE MICROELECTRÓNICA DE SEVILLA   (Spain)

Author keywords

[No Author keywords available]

Indexed keywords

COST FUNCTIONS; HEURISTIC ALGORITHMS; OPTIMIZATION; TIMING CIRCUITS; TREES (MATHEMATICS); ANALOG INTEGRATED CIRCUITS;

AUTOMATIC LAYOUT GENERATION; GLOBAL ROUTING; GLOBAL SYMMETRIES; INTERCONNECT PARASITICS; LOCAL SYMMETRY; PERFORMANCE-DRIVEN; PLACEMENT ALGORITHM; ROUTE OPTIMIZATION; COST-FUNCTION; KEY ISSUES; MEASUREMENTS OF; OPTIMIZATION ALGORITHMS;

ANALOG INTEGRATED CIRCUITS; HEURISTIC ALGORITHMS;

EID: 85029646146     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/edtc.1997.582389     Document Type: Conference Paper

References (10)

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