-
1
-
-
0025383839
-
OPASYN: A compiler for CMOS operational amplifiers
-
Feb.
-
H. Y. Koh, C. H. Sequin, and P. R. Gray, "OPASYN: A compiler for CMOS operational amplifiers,"IEEE Trans. Computer-Aided Design, vol. 9, pp. 113-126, Feb. 1990.
-
(1990)
IEEE Trans. Computer-Aided Design
, vol.9
, pp. 113-126
-
-
Koh, H.Y.1
Sequin, C.H.2
Gray, P.R.3
-
2
-
-
11244293822
-
Operational amplifier compilation with performance optimization
-
May 1989
-
H. Onodera, H. Kanbara, and K. Tamaru, "Operational amplifier compilation with performance optimization,"in Proc. IEEE CICC, May 1989, pp. 17.4.1-17.4.6.
-
Proc. IEEE CICC
, pp. 1741-1746
-
-
Onodera, H.1
Kanbara, H.2
Tamaru, K.3
-
3
-
-
11244352345
-
-
Carnegie Mellon Univ., Pittsburgh, PA, Res. Rep. CMUCAD-89-65, Nov.
-
R. Harjani, R. A. Rutenbar, and L. R. Carley, "OASYS. A framework for analog circuit synthesis," Carnegie Mellon Univ., Pittsburgh, PA, Res. Rep. CMUCAD-89-65, Nov. 1989.
-
(1989)
OASYS. a framework for analog circuit synthesis
-
-
Harjani, R.1
Rutenbar, R.A.2
Carley, L.R.3
-
4
-
-
0023030156
-
A methodology for automated layout of switched-capacitor filters
-
H. Yaghutiel, A. Sangiovanni-Vincentelli, and P. R. Gray, "A methodology for automated layout of switched-capacitor filters,"in Proc. IEEE 1CCAD, 1986, pp. 444-447.
-
Proc. IEEE 1CCAD, 1986
, pp. 444-447
-
-
Yaghutiel, H.1
Sangiovanni-Vincentelli, A.2
Gray, P.R.3
-
5
-
-
33747994753
-
A switched-capacitor filter compiler
-
Sept.
-
Y. Therasse, L. Reynders, R. Lannoo, and B. Dupont, "A switched-capacitor filter compiler,"VLSI Syst. Des., vol. 8, no. 10, pp. 85-88, Sept. 1987.
-
(1987)
VLSI Syst. Des.
, vol.8
, Issue.10
, pp. 85-88
-
-
Therasse, Y.1
Reynders, L.2
Lannoo, R.3
Dupont, B.4
-
6
-
-
0005387493
-
A switcheri-capaciror filter silicon compiler
-
Feb.
-
.1. Assael, P. Senn. and M. S. Tawfik, "A switcheri-capaciror filter silicon compiler," 1EEEJ. Solid-State Circuits, vol. 23, pp. 166-174, Feb. 1988.
-
(1988)
1EEEJ. Solid-State Circuits
, vol.23
, pp. 166-174
-
-
Senn, A.P.1
Tawfik, M.S.2
-
7
-
-
0022603355
-
A silicon compiler for successive approximation A/D and D/A converters
-
P. E. Alien and P. R. Barton. "A silicon compiler for successive approximation A/D and D/A converters,"in Proc. IEEE CICC, 1986, pp. 552-555.
-
Proc. IEEE CICC, 1986
, pp. 552-555
-
-
Alien, P.E.1
Barton, P.R.2
-
8
-
-
0025537037
-
CAD1CS-Cyclic analog-to-digital converter synthesis
-
Nov. 1990
-
G. Jusuf, P. R. Gray, and A. Sangiovanni-Vincentelli, "CAD1CS-Cyclic analog-to-digital converter synthesis,"in Proc. IEEE ICCAD, Nov. 1990, pp. 286-289.
-
Proc. IEEE ICCAD
, pp. 286-289
-
-
Jusuf, G.1
Gray, P.R.2
Sangiovanni-Vincentelli, A.3
-
9
-
-
0028044345
-
Top-down, constraint-driven methodology based generation of n-bit interpolative current source D/A converters
-
May 1994
-
H. Chang, E. Liu, R. Ncff, E. Felt, E. Malavasi, E. Charbon, A. Sangiovanni-Vincentelli, and P. R. Gray, "Top-down, constraint-driven methodology based generation of n-bit interpolative current source D/A converters,"in Proc. IEEE CICC, May 1994, pp. 369-372.
-
Proc. IEEE CICC
, pp. 369-372
-
-
Chang, H.1
Liu, E.2
Ncff, R.3
Felt, E.4
Malavasi, E.5
Charbon, E.6
Sangiovanni-Vincentelli, A.7
Gray, P.R.8
-
10
-
-
84869441603
-
Analogue macrocell assembler,' VLSI Syst. des
-
May
-
G. Winner etui., "Analogue macrocell assembler,' VLSI Syst. Des., vol. 8, no. 5, pp. 68-71, May 1987.
-
(1987)
Etui.
, vol.8
, Issue.5
, pp. 68-71
-
-
Winner, G.1
-
11
-
-
0022228170
-
Autorouted analog VLSI
-
C. D. Kimble, A. E. Dunlop, G. F. Gross, V. L. Hein, M. Y. Luong, K. J. Stern, and E. J. Swanson. "Autorouted analog VLSI,"in Proc. IEEE CICC. 1985, pp. 72-78.
-
Proc. IEEE CICC. 1985
, pp. 72-78
-
-
Kimble, C.D.1
Dunlop, A.E.2
Gross, G.F.3
Hein, V.L.4
Luong, M.Y.5
Stern, K.J.6
Swanson, E.J.7
-
12
-
-
0022706706
-
High-performance designs with CMOS analogue standard cells
-
Apr.
-
T. Pletersek et al., "High-performance designs with CMOS analogue standard cells," 1EEEJ. Solid-Slate Circuits, vol. 21, pp. 215-222, Apr. 1986.
-
(1986)
1EEEJ. Solid-Slate Circuits
, vol.21
, pp. 215-222
-
-
Pletersek, T.1
-
13
-
-
0024645861
-
A CMOS-based analog standard cell product family
-
Apr.
-
L. D. Smith etal., "A CMOS-based analog standard cell product family,"IEEEJ. Solid-State Circuits, vol. 24, pp. 370-379, Apr. 1989.
-
(1989)
IEEEJ. Solid-State Circuits
, vol.24
, pp. 370-379
-
-
Smith, L.D.1
-
14
-
-
0024647840
-
II AC: An automated layout tool for analog CMOS circuits
-
Apr.
-
J. Rijmenants, J. B. Litsios, T. R. Schwarz, and M. G. R. Degrauwe, "II AC: An automated layout tool for analog CMOS circuits,"IEEE J. Solid-Slate Circuits, vol. 24, pp. 417-125, Apr. 1989.
-
(1989)
IEEE J. Solid-Slate Circuits
, vol.24
, pp. 417-1125
-
-
Rijmenants, J.1
Litsios, J.B.2
Schwarz, T.R.3
Degrauwe, M.G.R.4
-
15
-
-
0024681330
-
Toward an analog system design environment
-
June
-
[15[ M. G. R. Degrauwe et al, "Toward an analog system design environment," IEEE J. Solid State Circuits, vol. 24, pp. 659-671. June 1989.
-
(1989)
IEEE J. Solid State Circuits
, vol.24
, pp. 659-671
-
-
Degrauwe, M.G.R.1
-
16
-
-
0347525615
-
SALIM: A layout generator tool for analog ICV in
-
May 1988
-
M. Kayal, S. Piguet, M. Declercq, and B. Hochet, "SALIM: A layout generator tool for analog ICV in Proc. IEEE CICC, May 1988, pp. 751-754.
-
Proc. IEEE CICC
, pp. 751-754
-
-
Kayal, M.1
Piguet, S.2
Declercq, M.3
Hochet, B.4
-
17
-
-
0024942776
-
LADIES: An automatic layout system for analog LSI's
-
Nov. 1989
-
M. Mogaki, N. Kalo, Y. Chikami, N. Yamada, and Y. Kobayashi, "LADIES: An automatic layout system for analog LSI's,"in Proc. IEEE ICCAD, Nov. 1989, pp. 450-453.
-
Proc. IEEE ICCAD
, pp. 450-453
-
-
Mogaki, M.1
Kalo, N.2
Chikami, Y.3
Yamada, N.4
Kobayashi, Y.5
-
18
-
-
0347525614
-
BLADES: An A. I. approach to analog circuit design
-
June
-
F. M. Turky and E. E. Perry, "BLADES: An A. I. approach to analog circuit design,"IEEE Trans. Computer-Aided Design, vol. 8, pp. 680-692, June 1989.
-
(1989)
IEEE Trans. Computer-Aided Design
, vol.8
, pp. 680-692
-
-
Turky, F.M.1
Perry, E.E.2
-
19
-
-
0024646662
-
A generalized approach to routing mixed analog and digital signal nets in a channel
-
Apr.
-
R. S. Gyurcsik and J.-C. Jeen, "A generalized approach to routing mixed analog and digital signal nets in a channel,"IEEEJ. Solid-State Circuits, vol. 24, pp. 436-442, Apr. 1989.
-
(1989)
IEEEJ. Solid-State Circuits
, vol.24
, pp. 436-442
-
-
Gyurcsik, R.S.1
Jeen, J.-C.2
-
20
-
-
0025545977
-
A routing system for mixed A/D standard cell LSI's
-
Nov. 1990
-
I. Harada, H. Kitazawa, and T. Kaneko, "A routing system for mixed A/D standard cell LSI's,"in Croc. IEEE ICCAD, Nov. 1990, pp. 378-381.
-
Croc. IEEE ICCAD
, pp. 378-381
-
-
Harada, I.1
Kitazawa, H.2
Kaneko, T.3
-
21
-
-
0026117896
-
A technology-independent approach to custom analog cell generation
-
Mar.
-
S. W. Mehranfar, "A technology-independent approach to custom analog cell generation,"IEEEJ. Solid-State Circuits, vol. 26, pp. 386-393, Mar. 1991.
-
(1991)
IEEEJ. Solid-State Circuits
, vol.26
, pp. 386-393
-
-
Mehranfar, S.W.1
-
22
-
-
0026118974
-
KOAN/ANAORAM II: New tools for device-level analog placement and routing
-
Mar.
-
J. M. Cohn, D. 1. Garrod, R. A. Rutenbar, and L. R. Carley, "KOAN/ANAORAM II: New tools for device-level analog placement and routing,"IEEE J. Solid-Stale Circuits, vol. 26, pp. 330-342, Mar. 1991.
-
(1991)
IEEE J. Solid-Stale Circuits
, vol.26
, pp. 330-342
-
-
Cohn, J.M.1
Garrod, D.2
Rutenbar, R.A.3
Carley, L.R.4
-
23
-
-
0024902637
-
An efficient algorithm for layout compaction problem with symmetry constraints
-
Nov. 1989
-
R. Okuda, T. Sato, H. Onodera, and K. Tamaru, "An efficient algorithm for layout compaction problem with symmetry constraints."in Proc. IEEE ICC AD, Nov. 1989, pp. 148-151.
-
Proc. IEEE ICC AD
, pp. 148-151
-
-
Okuda, R.1
Sato, T.2
Onodera, H.3
Tamaru, K.4
-
24
-
-
0025532052
-
Constraint-based channel routing for analog and mixed-analog digital circuits
-
Nov. 1990
-
U. Choudhtiry and A. Sangiovanni-Vincentelli, "Constraint-based channel routing for analog and mixed-analog digital circuits,"in Proc. IEEE ICCAD, Nov. 1990, pp. 198-201.
-
Proc. IEEE ICCAD
, pp. 198-201
-
-
Choudhtiry, U.1
Sangiovanni-Vincentelli, A.2
-
25
-
-
0025564139
-
A routing methodology for analog integrated circuits
-
Nov. 1990
-
E. Malavasi, U. Choudhury, and A. Sangiovanni-Vincentelli, "A routing methodology for analog integrated circuits,"in Proc. IEEE ICCAD, Nov. 1990, pp. 202-205.
-
Proc. IEEE ICCAD
, pp. 202-205
-
-
Malavasi, E.1
Choudhury, U.2
Sangiovanni-Vincentelli, A.3
-
27
-
-
0012118175
-
A constraint-driven placement methodology 1 for analog integrated circuits
-
May 1992
-
E. Charbon, E. Malavasi, U. Choudhury, A. Casotto, and A. Sangiovanni-Vincentelli, "A constraint-driven placement methodology 1 for analog integrated circuits,"in Proc. IEEE C1CC, May 1992, pp. 2821-2824.
-
Proc. IEEE C1CC
, pp. 2821-2824
-
-
Charbon, E.1
Malavasi, E.2
Choudhury, U.3
Casotto, A.4
Sangiovanni-Vincentelli, A.5
-
30
-
-
0000965412
-
A top-down, constraint-driven design methodology for analog integrated circuits
-
May 1992
-
H. Chang, A. Sangiovanni-Vincentelli, F. Balarin, E. Charbon, U. Choudhury, G. Jusuf, E. Liu, E. Malavasi, R. Neff, and P. Gray, "A top-down, constraint-driven design methodology for analog integrated circuits,"in Proc. IEEE CICC, May 1992, pp. 841-846.
-
Proc. IEEE CICC
, pp. 841-846
-
-
Chang, H.1
Sangiovanni-Vincentelli, A.2
Balarin, F.3
Charbon, E.4
Choudhury, U.5
Jusuf, G.6
Liu, E.7
Malavasi, E.8
Neff, R.9
Gray, P.10
-
32
-
-
33747997541
-
Performance driven compaction for analog integrated circuits
-
May
-
E. Felt, E. Malavasi, E. Charbon, R. Totaro, and A. Sangiovanni-Vincentelli, "Performance driven compaction for analog integrated circuits,"in Proc. IEEE CICC, May 1993, pp. 1731-1735.
-
(1993)
Proc. IEEE CICC
, pp. 1731-1735
-
-
Felt, E.1
Malavasi, E.2
Charbon, E.3
Totaro, R.4
Sangiovanni-Vincentelli, A.5
-
33
-
-
0028552981
-
Simultaneous placement and module optimization of analog IC's
-
June
-
E. Charbon, E. Malavasi, D. Pandini, and A. Sangiovanni-Vincentelli, "Simultaneous placement and module optimization of analog IC's,"in Proc. IEEE/ACM DAC. June 1994, pp. 31-35.
-
(1994)
Proc. IEEE/ACM DAC.
, pp. 31-35
-
-
Charbon, E.1
Malavasi, E.2
Pandini, D.3
Sangiovanni-Vincentelli, A.4
-
34
-
-
0029220994
-
Optimum CMOS stack generation with analog constraints
-
Jan.
-
E. Malavasi and Ü. Pandini, "Optimum CMOS stack generation with analog constraints,"IEEE Trans. Computer Aided Design, vol. 14, pp. 107-122, Jan. 1995.
-
(1995)
IEEE Trans. Computer Aided Design
, vol.14
, pp. 107-122
-
-
Malavasi, E.1
Pandini, Ü.2
-
35
-
-
0023994941
-
DELIGHT-SPICE: An optimization-based system for the design of integrated circuits
-
Apr.
-
W. Nye, D. C. Riley, A. Sangiovanni-Vincenlelli, and A. L. Tits, "DELIGHT-SPICE: An optimization-based system for the design of integrated circuits," IEEE Trans. Computer-Aided Design, vol. 7, pp. 501-519, Apr. 1988.
-
(1988)
IEEE Trans. Computer-Aided Design
, vol.7
, pp. 501-519
-
-
Nye, W.1
Riley, D.C.2
Sangiovanni-Vincenlelli, A.3
Tits, A.L.4
-
36
-
-
4244208485
-
Performance optimization of integrated circuits
-
Univ. California, Berkeley. CA
-
J.-M. Shyu, "Performance optimization of integrated circuits," Univ. California, Berkeley. CA, Memo. UCB/BRL M88/74, Nov. 1988.
-
(1988)
Memo. UCB/BRL M88/74, Nov.
-
-
Shyu, J.-M.1
-
37
-
-
0000208736
-
The generalized adjoint network and network sensitivities
-
Aug.
-
S. W. Director and R. A. Rohrer, "The generalized adjoint network and network sensitivities,"IEEE Trans. Circuit Theory1, vol. 16. pp. 318-323. Aug. 1969.
-
(1969)
IEEE Trans. Circuit Theory1
, vol.16
, pp. 318-323
-
-
Director, S.W.1
Rohrer, R.A.2
-
40
-
-
0024754187
-
Matching properties of MOS tiansistors
-
Oct.
-
M. J. M. Pelgrom, A. C. J. Duinmaijer, and A. P. G. Welbers, "Matching properties of MOS tiansistors,"IEEE J. Solid-State Circuits, vol. 24, pp. 1433-1440, Oct. 1989.
-
(1989)
IEEE J. Solid-State Circuits
, vol.24
, pp. 1433-1440
-
-
Pelgrom, M.J.M.1
Duinmaijer, A.C.J.2
Welbers, A.P.G.3
-
41
-
-
0028055460
-
Applying a submicron mismatch model to practical IC design
-
May 1994
-
C. Guardiani, A. Tomasini, J. Benkoski, M. Quarantelli, and P. Gubian, "Applying a submicron mismatch model to practical IC design,"in Proc. IEEE CICC, May 1994, pp. 297 300.
-
Proc. IEEE CICC
, pp. 297300
-
-
Guardiani, C.1
Tomasini, A.2
Benkoski, J.3
Quarantelli, M.4
Gubian, P.5
-
43
-
-
0027876719
-
Latchup-aware placement and parasitic-bounded routing of custom analog cells
-
Nov. 1993
-
R. Basaran, R. A. Rutenbar, and L. R. Carley, "Latchup-aware placement and parasitic-bounded routing of custom analog cells,"in Proc. IEEE ICCAD, Nov. 1993, pp. 415-421.
-
Proc. IEEE ICCAD
, pp. 415-421
-
-
Basaran, R.1
Rutenbar, R.A.2
Carley, L.R.3
-
44
-
-
0028016997
-
DORIC: Design of optimal and robust integrated circuits
-
May 1994
-
Z. Daoud and C. J. Spanos, "DORIC: Design of optimal and robust integrated circuits,"in Proc. IEEE CICC, May 1994, pp. 361-364.
-
Proc. IEEE CICC
, pp. 361-364
-
-
Daoud, Z.1
Spanos, C.J.2
-
46
-
-
0024142707
-
Chip-planning, placement and global routing of macro/custom cell IC's using simulated annealing
-
June 1988
-
C. Sechen and A. Sangiovanni-Vincentelli, "Chip-planning, placement and global routing of macro/custom cell IC's using simulated annealing,"in Proc. IEEE/ACM DAC, June 1988, pp. 73-80.
-
Proc. IEEE/ACM DAC
, pp. 73-80
-
-
Sechen, C.1
Sangiovanni-Vincentelli, A.2
-
47
-
-
0039643423
-
Channel routing
-
T. Ohtsuki, Ed. Amsterdam, The Netherlands: North Holland, 1986, ch. 1
-
M. Burstein, "Channel routing,"in Layout Design and Verification, T. Ohtsuki, Ed. Amsterdam, The Netherlands: North Holland, 1986, ch. 1, pp. 133-167.
-
Layout Design and Verification
, pp. 133-167
-
-
Burstein, M.1
-
48
-
-
0021177495
-
A global routing algorithm for general cells
-
G. W. Clow, "A global routing algorithm for general cells,"in Proc. IEEE/ACM DAC, 1984, pp. 45-51.
-
(1984)
Proc. IEEE/ACM DAC
, pp. 45-51
-
-
Clow, G.W.1
-
49
-
-
0026995131
-
An efficient methodology for symbolic compaction of analog IC's with multiple symmetry constraints
-
Sept.
-
E. Felt, E. Charbon, E. Malavasi, and A. Sangiovanni-Vincentelli, "An efficient methodology for symbolic compaction of analog IC's with multiple symmetry constraints,"in Proc. Euro. Design Automation Conf.. Sept. 1992, pp." 148-153.
-
(1992)
Proc. Euro. Design Automation Conf..
, pp. 148-153
-
-
Felt, E.1
Charbon, E.2
Malavasi, E.3
Sangiovanni-Vincentelli, A.4
-
50
-
-
0029344797
-
Symbolic compaction with analog constraints
-
July-Aug.
-
E. Malavasi, E. Felt, E. Charbon, and A. Sangiovanni-Vincentelli, "Symbolic compaction with analog constraints,"Int. J. Circuit Theory AppL. vol. 23, no. 4, pp. 433-4-52, July-Aug. 1995.
-
(1995)
Int. J. Circuit Theory AppL.
, vol.23
, Issue.4
-
-
Malavasi, E.1
Felt, E.2
Charbon, E.3
Sangiovanni-Vincentelli, A.4
-
51
-
-
0003212510
-
Analog module generators for silicon compilation
-
May
-
J. Kühn, "Analog module generators for silicon compilation,"VLSI Syst. Des., vol. 8, no. 5, pp. 74-80, May 1987.
-
(1987)
VLSI Syst. Des.
, vol.8
, Issue.5
, pp. 74-80
-
-
Kühn, J.1
-
52
-
-
0026406873
-
An analytical-model generator for interconnect capacitances
-
May
-
U. Choudhury and A. Sangiovanni-Vincentelli, "An analytical-model generator for interconnect capacitances,"in Proc. IEEE CICC, May 1991, pp. 861-864.
-
(1991)
Proc. IEEE CICC
, pp. 861-864
-
-
Choudhury, U.1
Sangiovanni-Vincentelli, A.2
|