O(n) algorithm for transistor stacking with performance constraints

Proceedings - Design Automation Conference

Volumn , Issue , 1996, Pages 221-226

  Basaran, Bulent ^a   Rutenbar, Rob A ^a  

^a CARNEGIE MELLON UNIVERSITY   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

ALGORITHMS; CONSTRAINT THEORY; INTEGRATED CIRCUIT LAYOUT; TRANSISTORS;

ANALOG SPECIFIC PERFORMANCE CONSTRAINTS; EULERIAN TRAIL FINDING ALGORITHM; TIME COMPLEXITY; TRANSISTOR STACKING;

CMOS INTEGRATED CIRCUITS;

EID: 0029697870     PISSN: 0738100X     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (18)