Algorithm and Architecture for a Low-Power Content-Addressable Memory Based on Sparse Clustered Networks

IEEE Transactions on Very Large Scale Integration (VLSI) Systems

Volumn 23, Issue 4, 2015, Pages 642-653

  Jarollahi, Hooman ^a   Gripon, Vincent ^b   Onizawa, Naoya ^c   Gross, Warren J ^a  

^a MCGILL UNIVERSITY   (Canada)

^b ECOLE DES MINES DE NANTES   (France)

^c TOHOKU UNIVERSITY   (Japan)

Author keywords

Associative memory; content addressable memory (CAM); low power computing; recurrent neural networks; sparse clustered networks (SCNs)

Indexed keywords

ALGORITHMS; ASSOCIATIVE PROCESSING; BUDGET CONTROL; CMOS INTEGRATED CIRCUITS; DESIGN; ENERGY UTILIZATION; LOW POWER ELECTRONICS; NETWORK ARCHITECTURE; RECURRENT NEURAL NETWORKS;

ASSOCIATIVE MEMORY; CLUSTERED NETWORKS; DESIGN METHODOLOGY; DYNAMIC ENERGY CONSUMPTION; LOW-POWER COMPUTING; PARALLEL COMPARISONS; PERFORMANCE REQUIREMENTS; PROPOSED ARCHITECTURES;

ASSOCIATIVE STORAGE;

EID: 85027929115     PISSN: 10638210     EISSN: None     Source Type: Journal    
DOI: 10.1109/TVLSI.2014.2316733     Document Type: Article

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