A 65 nm 0.165 fJ/bit/search 256 × 144 TCAM macro design for IPv6 lookup tables

IEEE Journal of Solid-State Circuits

Volumn 46, Issue 2, 2011, Pages 507-519

  Huang, Po Tsang ^a   Hwang, Wei ^a  

^a NATIONAL CHIAO TUNG UNIVERSITY   (Taiwan)

Author keywords

Butterfly match line; hierarchy search line; memory; power gating; TCAM; XOR conditional keeper

Indexed keywords

HIERARCHY SEARCH-LINE; MATCH LINE; MEMORY; POWER GATING; TCAM; XOR CONDITIONAL KEEPER;

CMOS INTEGRATED CIRCUITS; DESIGN; ENERGY UTILIZATION; INTERNET PROTOCOLS; LEAKAGE CURRENTS; LOGIC GATES; MACROS; MICROPROCESSOR CHIPS; NETWORK ARCHITECTURE; TABLE LOOKUP;

TERNARY CONTENT ADRESSABLE MEMORY;

EID: 79551568056     PISSN: 00189200     EISSN: None     Source Type: Journal    
DOI: 10.1109/JSSC.2010.2082270     Document Type: Article

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