Memory-aware scheduling of multicore task sets for real-time systems

Proceedings - 18th IEEE International Conference on Embedded and Real-Time Computing Systems and Applications, RTCSA 2012 - 2nd Workshop on Cyber-Physical Systems, Networks, and Applications, CPSNA

Volumn , Issue , 2012, Pages 300-309

  Bak, Stanley ^a   Yao, Gang ^a   Pellizzoni, Rodolfo ^b   Caccamo, Marco ^a  

^a UNIVERSITY OF ILLINOIS AT URBANA CHAMPAIGN   (United States)

^b UNIVERSITY OF WATERLOO   (Canada)

Author keywords

benchmark; eembc; least laxity first; M LAX; multicore; predictable execution model; PREM; real time scheduling; scheduling; simulation; simulator; tdma

Indexed keywords

BENCHMARK; EEMBC; EXECUTION MODEL; LEAST-LAXITY FIRST; M-LAX; MULTI CORE; PREM; REAL TIME SCHEDULING; SIMULATION;

DIGITAL STORAGE; EMBEDDED SYSTEMS; MICROPROCESSOR CHIPS; REAL TIME SYSTEMS; SCHEDULING; SIMULATORS; TIME DIVISION MULTIPLE ACCESS;

MULTITASKING;

EID: 84869006602     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/RTCSA.2012.48     Document Type: Conference Paper

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