Efficient Scheduling of Internet Banner Advertisements

ACM Transactions on Internet Technology

Volumn 3, Issue 4, 2003, Pages 334-346

  Amiri, Ali ^a   Menon, Syam ^b  

^a OKLAHOMA STATE UNIVERSITY   (United States)

^b UNIVERSITY OF TEXAS AT DALLAS   (United States)

Author keywords

Algorithms; Banner advertising; Management; Scheduling; WWW

Indexed keywords

EID: 85011106926     PISSN: 15335399     EISSN: 15576051     Source Type: Journal    
DOI: 10.1145/945846.945848     Document Type: Article

References (31)

1. Arnold, R., Mueller, F., and Whalley, D. 1994. Bounding worst-case instruction cache performance. In Proceedings of the Fifteenth IEEE Real-time Systems Symposium, San Juan. IEEE Computer Society Press., 172-181.
2. Benitez, M. 1994. Retargetable register allocation. Ph. D. thesis, University of Virginia, Charlottesville, VA.
3. Benitez, M. E. and Davidson, J. W. 1988. A portable global optimizer and linker. In Proceedings of the SIGPLAN'88 conference on Programming Language design and Implementation, Atlanta, GA. ACM Press, New York., 329-338.
4. Benitez, M. E. and Davidson, J. W. 1994. The advantages of machine-dependent global optimization. In Proceedings of the 1994 International Conference on Programming Languages and Architectures, 105-124.
5. Calder, B. and Grunwald, D. 1994. Reducing branch costs via branch alignment. In Proceeding ofASPLOS'94, San Jose, CA. ACM Press, New York., 242-251.
6. Engblom, J. and Ermedahl, A. 2000. Modeling complex flows for worst-case execution time analysis. In Proceedings of the 21st IEEE Real-time System Symposium, Orlando, FL. IEEE Computer Society Press, 875-889.
7. Eyre, J. and Bier, J. 1998. Dsp processors hit the mainsteam. IEEE Computer 31, 8, (Aug.), 51-59. Harmon, M., Baker, T., and Whalley, D. 1994. A retargetable technique for prediction execution time of code segments. Real-Time Systems. 159-182.
8. Healy, C. and Whalley, D. 1999. Tighter timing predictions by automatic detection and exploitation of value-dependent constraints. In Proceedings of the IEEE Real-Time Technology and Applications Symposium, Vancouver. IEEE Computer Society Press. 79-99.
9. Healy, C. and Whalley, D. 2000. Automatic detection and exploitation of branch constraints for timing analysis. IEEE Transaction on Software Engineering 28, 8 (Aug.), 763-781.
10. Healy, C., Whalley, D., and Harmon, M. 1995. Integrating the timing analysis of pipelining and instruction caching. In Proceedings of the Sixteenth IEEE Real-Time Systems Symposium, Pisa. IEEE Computer Society Press. 288-297.
11. Healy, C., Arnold, R., Mueller, F., Whalley, D., and Harmon, M. 1999. Bounding pipeline and instruction cache performance. IEEE Transactions on Computers 48, 1 (Jan.), 53-70.
12. Healy, C., Sjodin, M., Rustagi, V., Whalley, D., and van engelen, R. 2000a. Supporting timing analysis by automatic bounding of loop iterations. Real-Time Systems 18, 2 (May), 121-148.
13. Healy, C., WHALLEY, D., AND VANENGELEN, R. 2000b. Ageneralapproachfortighttimingpredictions of non-rectangular loops. In WIP Proceedings of the IEEE Real-Time Technology and Applications Symposium, Washington, DC. IEEE Computer Society Press., 11-14.
14. Hong, S. and Gerber, R. 1993. Compiling real-time programs into schedulable code. In Proceedings of the SIGPLAN'93, Albuquerque, NM. ACM Press, New York., 166-176.
15. Ko, L., Healy, C., Ratliff, E., Arnold, R., Whalley, D., and Harmon, M. 1996. Supporting the specification and analysis of timing constraints. In Proceeding of the IEEE Real-Time Technology and Application Symposium, Boston, MA. IEEE Computer Society Press., 170-178.
16. Ko, L., Al-Yaqoubi, N., Healy, C., Ratliff, E., Arnold, R., Whalley, D., and Harmon, M. 1999. Timing constraint specification and analysis. Software Practice & Experience 29, 1 (Jan.), 77-98.
17. Kulkarni, P., Zhao, W., Moon, H., Cho, K., Whalley, D., Davidson, J., Bailey, M., Paek, Y. and Gallivan, K. 2003. Finding effective optimization phase sequences. In ACM SIGPLAN Conference on Languages, Compilers, and Tools for Embedded Systems, San Diego, CA. ACM Press, New York., 12-23.
18. Lee, S., Lee, J., Park, C., and Min, S. 2004. A flexible tradeoff between code size and wcet using a dual instruction set processor. In International Workshop on Software and Compilers for Embedded Systems, Amsterdam. Springer, New york., 244-258.
19. Li, Y., Malik, S., and Wolfe, A. 1995. Efficient microarchitecture modeling and path analysis for real-time software. In Proceedings of the Sixteenth IEEE Real-time Systems Symposium, Pisa. IEEE Computer Society Press., 298-307.
20. Lim, S., Bae, Y., Jang, G., Rhee, B., Min, S., Park, C., Shin, H., Park, K., and Kim, C. 1994. An accurate worst case timing analysis technique for risc processors. In Proceedings of the Fifteenth IEEE Real-Time Systems Symposium, San Juan. IEEE Computer Society Press., 875-889.
21. Lundqvist, T. and Stenstrom, P. 1998. Integrating path and timing analysis using instruction-level simulation techniques. In Proceedings of SIGPLAN Workshop on Languages, Compilers and Tools for Embedded Systems(LCTES'98), Montreal. IEEE Computer Society Press., 1-15.
22. Mcfarling, S. and Hennessy, J. 1986. Reducing the cost of branches. In 13th Annual International Symposium of Computer Architecture, Tokyo, Japan. 396-403.-
23. Mueller, F. 1997. Timing predictions for multi-level caches. In ACM SIGPLAN Workshop on Language, Compiler and Tool Support for Real-time Systems, Las Vegas, NV. ACM Press, New York., 29-36.
24. Mueller, F. 2000. Timing analysis for instruction caches. Real-Time Systems 18, 2 (May), 209-239.
25. Pettis, K. and hansen, R. 1990. Profile guided code position. In Proceeding of the ACM SIGPLAN90 Conference on Programming Language Design and Implementation, ACM Press, New York., 16-27.
26. Shaw, A. C. 1989. Reasoning about time in higher-level language software. IEEE Transactions on Software Engineering 15, 7, 875-889.
27. T. S. M. Marlowe, 1992. Safe optimization for hard real-time programming. In Special Session on Real-Time Programming, Second International Conference on Systems Integration. 438-446.
28. Vivancos, E., Healy, C., Mueller, F., and Whalley, D. 2001. Parametric timing analysis. In Proceedings of the ACM SIGPLAN Workshop on Language, Compilers, and Tools for Embedded Systems, Snowbird, UT. ACM Press, New York., 83-93.
29. White, R. T., Mueller, F., Healy, C., Whalley, D., and Harmon, M. 1997. Timing analysis for data caches and set-associative caches. In Proceedings of the IEEE Real-Time Technology and Application Symposium, Montreal. IEEE Computer Society Press., 192-202.
30. White, R., Mueller, F., Healy, C., Whalley, D., and Harmon, M. 1999. Timing analysis for data caches and wrap-around-fill caches. Real-Time Systems 17, 1 (Nov.), 209-233.
31. Zhao, W., Cai, B., Whalley, D., Bailey, M., vanEngelen, R., Yuan, X., Hiser, J., Davidson, J., Gallivan, K., and Jones, D. 2002. Vista: A system for interactive code improvement. In ACM SIGPLAN Conference on Languages, Compilers, and Tools for Embedded Systems, Berlin. ACM Press, New York., 155-164.