A flexible tradeoff between code size and WCET using a dual instruction set processor

Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics)

Volumn 3199, Issue , 2004, Pages 244-258

  Lee, Sheayun ^a   Lee, Jaejin ^a   Park, Chang Yun ^b   Min, Sang Lyul ^a  

^a Seoul National University   (South Korea)

^b Chung Ang University   (South Korea)

Author keywords

[No Author keywords available]

Indexed keywords

APPLICATION PROGRAMS; CODES (SYMBOLS); PROGRAM COMPILERS; PROGRAM PROCESSORS; REAL TIME SYSTEMS;

EXECUTION SPEED; INSTRUCTION SET PROCESSORS; MULTIPLE APPLICATIONS; PERFORMANCE CRITERION; REDUCED INSTRUCTION SETS; TRADE-OFF RELATIONSHIP; WORST-CASE EXECUTION TIME; WORST-CASE PERFORMANCE;

EMBEDDED SYSTEMS;

EID: 35048900166     PISSN: 03029743     EISSN: 16113349     Source Type: Book Series    
DOI: 10.1007/978-3-540-30113-4_18     Document Type: Article

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