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Volumn 1474, Issue , 1998, Pages 1-15
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Integrating path and timing analysis using instruction-level simulation techniques
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Author keywords
[No Author keywords available]
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Indexed keywords
COMPUTATIONAL LINGUISTICS;
DATA HANDLING;
PROGRAM COMPILERS;
ARCHITECTURE SIMULATION;
BENCHMARK PROGRAMS;
HARDWARE PLATFORM;
INSTRUCTION LEVEL SIMULATION;
INSTRUCTION-LEVEL;
MULTI-LEVEL MEMORY HIERARCHY;
SIMULATION TECHNIQUE;
WORST-CASE EXECUTION TIME;
EMBEDDED SYSTEMS;
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EID: 84958986479
PISSN: 03029743
EISSN: 16113349
Source Type: Book Series
DOI: 10.1007/BFb0057776 Document Type: Conference Paper |
Times cited : (28)
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References (17)
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