A 500MHz multi-banked compilable DRAM macro with direct write and programmable pipelining

Digest of Technical Papers - IEEE International Solid-State Circuits Conference

Volumn 47, Issue , 2004, Pages

  Barth, J ^a,b   Anand, D ^a   Dreibelbis, J ^a   Fifield, J ^a   Gorman, K ^a   Nelms, M ^a   Pomichter, G ^a   Pontius, D ^a  

^a IBM MICROELECTRONICS   (United States)

^b IBM   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

BIT SWITCH DELAY SYSTEMS; RANDOM ADDRESS PATTERNS; RANDOM BANK CYCLE TIME; SIGNAL DEVELOPMENT;

BANDWIDTH; DATA TRANSFER; ELECTRIC POTENTIAL; PIPELINE PROCESSING SYSTEMS; PROGRAM COMPILERS; STATIC RANDOM ACCESS STORAGE;

DYNAMIC RANDOM ACCESS STORAGE;

EID: 2442646316     PISSN: 01936530     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (3)

1. J. Barth, et al., "A 300MHz Multi-Banked DRAM Macro Featuring GND Sense, Bit-Line Twisting and Direct Reference Cell Write," ISSCC Dig. Tech. Papers, pp. 156-157, Feb. 2002.
2. Y. Taito, et al., "A High Density Memory for SoC with a 143MHz SRAM Interface Using Sense- Synchronized-Read/Write," ISSCC Dig. Tech. Papers, pp.306-307, Feb. 2003.
3. H. Pilo, et al., "A 5.6ns Random Cycle 144Mb DRAM with 1.4Gb/s/pin and DDRS-SRAM Interface," ISSCC Dig. Tech. Papers, vol. XLVI, pp 308-309 Feb. 2003.