A 5.6-ns random cycle 144-Mb DRAM with 1.4 Gb/s/pin and DDR3-SRAM interface

IEEE Journal of Solid-State Circuits

Volumn 38, Issue 11, 2003, Pages 1974-1980

  Pilo, Harold ^a   Anand, Darren ^a   Barth, John ^a   Burns, Steve ^a   Corson, Phil ^a   Covino, Jim ^a   Lamphier, Steve ^a  

^a IBM MICROELECTRONICS   (United States)

Author keywords

Cache memory; DDR SRAM; Embedded DRAM; High performance DRAM; Memory

Indexed keywords

BUFFER STORAGE; CMOS INTEGRATED CIRCUITS; ELECTRIC POWER SUPPLIES TO APPARATUS; ELECTRONICS PACKAGING; INTEGRATED CIRCUIT MANUFACTURE; INTERFACES (MATERIALS); STATIC RANDOM ACCESS STORAGE;

DOUBLE DATA RATE; EARLY-WRITE SENSING TECHNIQUE; LOGIC-BASED PROCESS; PLASTIC BALL GRID ARRAY PACKAGE;

DYNAMIC RANDOM ACCESS STORAGE;

EID: 0242636496     PISSN: 00189200     EISSN: None     Source Type: Journal    
DOI: 10.1109/JSSC.2003.818141     Document Type: Article

References (5)

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2. H. Pilo et al., "An 833 MHz 1.5 W 18 Mb CMOS SRAM with 1.67 Gb/s/pin," in IEEE Int. Solid-State Circuits Conf. Dig. Tech. Papers, Feb. 2000, pp. 266-267.
3. C. Yoo et al., "A 1.8 V 700 Mb/s/pin 512 Mb DDR-II SDRAM with on-die termination and off-chip driver calibration," in IEEE Int. Solid-State Circuits Conf. Dig. Tech. Papers, Feb. 2003, pp. 312-313.
4. J. Barth et al., "A 300 MHz multi-banked eDRAM macro featuring GND sense, bit-line twisting and direct reference cell write," in IEEE Int. Solid-State Circuits Conf. Dig. Tech. Papers, Feb. 2002, pp. 156-157.
5. 2RAM)," in IEEE Int. Solid-State Circuits Conf. Dig. Tech. Papers, Feb. 2000, pp. 392-393.