A high density memory for SoC with a 143MHz SRAM interface using sense-synchronized-read/write

Digest of Technical Papers - IEEE International Solid-State Circuits Conference

Volumn , Issue , 2003, Pages

  Taito, Yasuhiko ^a   Tanizaki, Tetsushi ^a   Kinoshita, Mitsuya ^a   Igaue, Futoshi ^a   Fujino, Takeshi ^a   Arimoto, Kazutami ^a  

^a MITSUBISHI ELECTRIC CORPORATION   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

AMPLIFIERS (ELECTRONIC); CMOS INTEGRATED CIRCUITS; DELAY CIRCUITS; DIGITAL SIGNAL PROCESSING; ELECTRIC POWER SUPPLIES TO APPARATUS; FLIP FLOP CIRCUITS; GATES (TRANSISTOR); INTEGRATED CIRCUIT LAYOUT; INTERFACES (COMPUTER); LOGIC CIRCUITS; MOSFET DEVICES; STATIC RANDOM ACCESS STORAGE;

COLUMN SELECT LINE FOR WRITE; CROSS COUPLED CIRCUITS; HIGH DENSITY MEMORY; SENSE SYNCHRONIZED READ WRITE SCHEME; SYSTEM ON CHIP; WRITE DATA BUSES;

DYNAMIC RANDOM ACCESS STORAGE;

EID: 0037969031     PISSN: 01936530     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (3)

1. 2RAM)," ISSCC Digest of Technical Papers, pp.392-393, 2000.
2. Hwang, C., et al., "A 2.9ns Random Access Cycle Embedded DRAM with a Destructive-Read Architecture," Symposium on VLSI Circuits Digest of Technical Papers, pp.174-175, 2002.
3. Yamazaki, A., et al., "A 56.8GB/s 0.18μm Embedded DRAM Macro with Dual Port Sense Amplifier for 3D Graphics Controller," ISSCC Digest of Technical Papers, pp.394-395, 2000.