A 64B CPU pair: Dual- and single-processor chips

Digest of Technical Papers - IEEE International Solid-State Circuits Conference

Volumn , Issue , 2006, Pages

  Cohen, E B ^a   Rohrer, N J ^a   Sandon, P ^a   Canada, M ^a   Lichtenau, C ^b   Ringler, M ^a   Kartschoke, P ^a   Floyd, R ^a   Heaslip, J ^a   Ross, M ^a   Pflueger, T ^b   Hilgendorf, R ^a   McCormick, P ^a   Salem, G ^a   Connor, J ^a   Geissler, S ^a   Thygesen, D ^a  

^a IBM   (United States)

^b IBM   (Germany)

Author keywords

[No Author keywords available]

Indexed keywords

CACHE DESIGN; PROCESSOR INTERCONNECT BUS; SINGLE-PROCESSOR CHIP;

CACHE MEMORY; MICROPROCESSOR CHIPS; POWER ELECTRONICS;

PROGRAM PROCESSORS;

EID: 34347252038     PISSN: 01936530     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (5)