Power, area, and performance optimization of standard cell memory arrays through controlled placement

ACM Transactions on Design Automation of Electronic Systems

Volumn 21, Issue 4, 2016, Pages

  Teman, Adam ^a,b   Rossi, Davide ^c   Meinerzhagen, Pascal ^b   Benini, Luca ^c,d   Burg, Andreas ^a  

^a EPFL   (Switzerland)

^b BAR ILAN UNIVERSITY   (Israel)

^c UNIVERSITY OF BOLOGNA   (Italy)

^d ETH ZURICH   (Switzerland)

Author keywords

Controlled placement; Low power; Power area performance trade off; Standard cell memories; Subthreshold operation

Indexed keywords

ASPECT RATIO; BENCHMARKING; DESIGN; ECONOMIC AND SOCIAL EFFECTS; ENERGY EFFICIENCY; FOUNDRIES; INTEGRATED CIRCUIT DESIGN; MEMORY ARCHITECTURE; RANDOM ACCESS STORAGE; SILICON; SILICON ON INSULATOR TECHNOLOGY;

CONTROLLED PLACEMENT; LOW POWER; PERFORMANCE TRADE-OFF; STANDARD CELL; SUBTHRESHOLD OPERATION;

STATIC RANDOM ACCESS STORAGE;

EID: 84974602988     PISSN: 10844309     EISSN: 15577309     Source Type: Journal    
DOI: 10.1145/2890498     Document Type: Article

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