Dual-VT 4kb sub-VT memories with <1 pW/bit leakage in 65 nm CMOS

European Solid-State Circuits Conference

Volumn , Issue , 2013, Pages 197-200

  Andersson, Oskar ^a   Mohammadi, Babak ^a   Meinerzhagen, Pascal ^b   Burg, Andreas ^b   Rodrigues, Joachim Neves ^a  

^a LUND UNIVERSITY   (Sweden)

^b EPFL   (Switzerland)

Author keywords

[No Author keywords available]

Indexed keywords

65NM CMOS TECHNOLOGY; MEASUREMENTS OF; MEMORY COMPILERS; SPEED INCREASE; STANDARD-CELL; STORAGE CELLS; STORAGE ELEMENTS; SUBTHRESHOLD;

CMOS INTEGRATED CIRCUITS;

EID: 84891114305     PISSN: 19308833     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ESSCIRC.2013.6649106     Document Type: Conference Paper

References (11)

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10. P.-Y. Chang et al., "A 4R/2W register file design for UDVS microprocessors in 65-nm cmos," IEEE TCAS-II, 2012.
11. S. Clerc et al., "A 65nm SRAM achieving 250mV retention and 350mV, 1MHz, 55fJ/bit access energy, with bit-interleaved radiation soft error tolerance," in Proc. IEEE ESSCIRC, 2012.