-
1
-
-
0027192667
-
Column-associative caches: A technique for reducing the miss rate of direct-mapped caches
-
(San Diego, CA, May)
-
Agarwal, A. and Pudar, S. D. 1993. Column-associative caches: A technique for reducing the miss rate of direct-mapped caches. In ISCA-93: ACM/IEEE International Symposium on Computer Architecture (San Diego, CA, May), 179-180
-
(1993)
In ISCA-93: ACM/IEEE International Symposium on Computer Architecture
, pp. 179-180
-
-
Agarwal, A.1
Pudar, S.D.2
-
2
-
-
0035334798
-
A bitline leakage compensation scheme for low-voltage SRAMs
-
Agawa, K., Hara, H., Takayanagi, T., and Kuroda, T. 2001. A bitline leakage compensation scheme for low-voltage SRAMs. IEEE J. Solid-State Circuits 36, 5, 726-734
-
(2001)
IEEE J. Solid-State Circuits
, vol.36
, Issue.5
, pp. 726-734
-
-
Agawa, K.1
Hara, H.2
Takayanagi, T.3
Kuroda, T.4
-
3
-
-
0032136258
-
A replica technique for wordline and sense control in low-power SRAMs
-
Amrutur, B. and Horowitz, M. 1998. A replica technique for wordline and sense control in low-power SRAMs. IEEE J. Solid-State Circuits 32, 8, 1208-1219
-
(1998)
IEEE J. Solid-State Circuits
, vol.32
, Issue.8
, pp. 1208-1219
-
-
Amrutur, B.1
Horowitz, M.2
-
5
-
-
0031642231
-
Power and performance tradeoffs using various caching strategies
-
(Monterey, CA, Aug.)
-
Bahar, R. I., Albera, G., and Manne, S. 1998. Power and performance tradeoffs using various caching strategies. In ISLPED-98: ACM/IEEE International Symposium on Low Power Electronics and Design (Monterey, CA, Aug.), 64-69
-
(1998)
ISLPED-98: ACM/IEEE International Symposium on Low Power Electronics and Design
, pp. 64-69
-
-
Bahar, R.I.1
Albera, G.2
Manne, S.3
-
6
-
-
0031366763
-
Instruction buffering to reduce power in processors for signal processing
-
(Dec.)
-
Bajwa, R. S., Hiraki, M., Kojima, H., Gorny, D. J., Nitta, K., Shridhar, A., Seki, K., and Sasaki, K. 1998. Instruction buffering to reduce power in processors for signal processing. IEEE Trans. VLSI Syst. 5, 4 (Dec.), 417-424
-
(1998)
IEEE Trans. VLSI Syst.
, vol.5
, pp. 417-424
-
-
Bajwa, R.S.1
Hiraki, M.2
Kojima, H.3
Gorny, D.J.4
Nitta, K.5
Shridhar, A.6
Seki, K.7
Sasaki, K.8
-
7
-
-
0033359508
-
Selective instruction compression for memory energy reduction in embedded systems
-
(San Diego, CA, Aug.)
-
Benini, L., Macii, A., Macii, E., and Poncino, M. 1999. Selective instruction compression for memory energy reduction in embedded systems. In ISLPED-99: ACM/IEEE International Symposium on Low Power Electronics and Design (San Diego, CA, Aug.), 206-211
-
(1999)
ISLPED-99: ACM/IEEE International Symposium on Low Power Electronics and Design
, pp. 206-211
-
-
Benini, L.1
Macii, A.2
Macii, E.3
Poncino, M.4
-
8
-
-
0038450768
-
-
Kluwer, Dordrecht
-
Benini, L., Macii, A., and Poncino, M. 2002. Memory Design Techniques for Low-Energy Embedded Systems, Kluwer, Dordrecht
-
(2002)
Memory Design Techniques for Low-Energy Embedded Systems
-
-
Benini, L.1
Macii, A.2
Poncino, M.3
-
9
-
-
0035274630
-
A 64-Min single-chip voice recorder/player using embedded 4-b/cell FLASH memory
-
Borgatti, M., et al. 2001. A 64-Min single-chip voice recorder/player using embedded 4-b/cell FLASH memory. IEEE J. Solid-State Circuits 36, 3, 516-521
-
(2001)
IEEE J. Solid-State Circuits
, vol.36
, Issue.3
, pp. 516-521
-
-
Borgatti, M.1
-
10
-
-
0004070915
-
Hardware techniques to improve the performance of the processor/memory interface
-
Ph.D. dissertation, Univ. of Wisconsin-Madison
-
Burger, D. C. 1998. Hardware techniques to improve the performance of the processor/memory interface, Ph.D. dissertation, Univ. of Wisconsin-Madison
-
(1998)
-
-
Burger, D.C.1
-
11
-
-
0031277174
-
Limited bandwidth to affect processor design
-
Burger, D. C., Goodman, J. R., and Kagle, A. 1997. Limited bandwidth to affect processor design. IEEE Micro 17, 6, 55-62
-
(1997)
IEEE Micro
, vol.17
, Issue.6
, pp. 55-62
-
-
Burger, D.C.1
Goodman, J.R.2
Kagle, A.3
-
12
-
-
0004038844
-
-
Kluwer, Dordrecht
-
Cappelletti, P., Golla, C., Olivo, P., and Zanoni, E. 1999. Flash Memories, Kluwer, Dordrecht
-
(1999)
Flash Memories
-
-
Cappelletti, P.1
Golla, C.2
Olivo, P.3
Zanoni, E.4
-
13
-
-
0003939345
-
-
IEEE Press, New York
-
Chandrakasan, A., Bowhill, W., and Fox, F. 2001. Design of High-Performance Microprocessor Circuits, IEEE Press, New York
-
(2001)
Design of High-Performance Microprocessor Circuits
-
-
Chandrakasan, A.1
Bowhill, W.2
Fox, F.3
-
14
-
-
85025389209
-
High flexibility CMOS SRAM generator using multiplan architecture
-
Clerc, S., Dufourt, D., and Zangara, L. 1999. High flexibility CMOS SRAM generator using multiplan architecture. In IEEEASIC/SOC Conference, 414-417
-
(1999)
IEEEASIC/SOC Conference
, pp. 414-417
-
-
Clerc, S.1
Dufourt, D.2
Zangara, L.3
-
15
-
-
0003819233
-
Modeling memory organizations for the synthesis of low power systems
-
Carnegie Mellon Univ
-
Coumeri, S. L. 1999. Modeling memory organizations for the synthesis of low power systems, Ph.D. dissertation, EE and CS Dept., Carnegie Mellon Univ
-
(1999)
Ph.D. dissertation, EE and CS Dept.
-
-
Coumeri, S.L.1
-
16
-
-
0031622061
-
Memory modeling for system synthesis
-
(Monterey, CA, Aug.)
-
Coumeri, S. L. and Thomas, D. E. 1998. Memory modeling for system synthesis. In ISLPED-98: ACM/IEEE International Symposium on Low Power Electronics and Design (Monterey, CA, Aug.), 179-184
-
(1998)
ISLPED-98: ACM/IEEE International Symposium on Low Power Electronics and Design
, pp. 179-184
-
-
Coumeri, S.L.1
Thomas, D.E.2
-
17
-
-
85025381769
-
Exotic memories
-
(Apr.)
-
Dipert, B. 2001a. Exotic memories. EDN Mag. (Apr.)
-
(2001)
EDN Mag.
-
-
Dipert, B.1
-
18
-
-
0035936070
-
Banish bad memories
-
(Nov.)
-
Dipert, B. 2001b. Banish bad memories. EDN Mag. (Nov.)
-
(2001)
EDN Mag.
-
-
Dipert, B.1
-
19
-
-
0029235765
-
Memory segmentation to exploit sleep mode operation
-
(San Francisco, CA, June)
-
Farrahi, A., Tellez, G., and Sarrafzadeh, M. 1995. Memory segmentation to exploit sleep mode operation. In DAC-32: ACM/IEEE Design Automation Conference (San Francisco, CA, June), 36-41
-
(1995)
DAC-32: ACM/IEEE Design Automation Conference
, pp. 36-41
-
-
Farrahi, A.1
Tellez, G.2
Sarrafzadeh, M.3
-
20
-
-
0033297667
-
The non-critical buffer: using load latency tolerance to improve data cache efficiency
-
(Austin, TX, Oct.)
-
Fisk, B. R. and Bahar, R. I. 1999. The non-critical buffer: using load latency tolerance to improve data cache efficiency. In ICCD-99: IEEE International Conference on Computer Design (Austin, TX, Oct.), 538-545
-
(1999)
ICCD-99: IEEE International Conference on Computer Design
, pp. 538-545
-
-
Fisk, B.R.1
Bahar, R.I.2
-
21
-
-
33646900503
-
Device scaling limits of Si MOSFETs and their application dependencies
-
Frank, D., Dennard, R., Novak, E., Solomon, P., Taur, Y., and Wong, H. S. 2001. Device scaling limits of Si MOSFETs and their application dependencies. Proc. IEEE 89, 3, 259-288
-
(2001)
Proc. IEEE
, vol.89
, Issue.3
, pp. 259-288
-
-
Frank, D.1
Dennard, R.2
Novak, E.3
Solomon, P.4
Taur, Y.5
Wong, H.S.6
-
22
-
-
4544327926
-
MoSys explains 1T-SRAM technology, Microprocess
-
Glaskowsky, P. 1999. MoSys explains 1T-SRAM technology, Microprocess. Rep. 13, 12
-
(1999)
Rep.
, vol.13
, pp. 12
-
-
Glaskowsky, P.1
-
23
-
-
0029204095
-
A data-cache with multiple caching strategies tuned to different types of locality
-
(Barcelona, Spain, July)
-
Gonzalez, A., Aliagas, C., and Valero, M. 1995. A data-cache with multiple caching strategies tuned to different types of locality. In ICS-95: ACM International Conference on Supercomputing (Barcelona, Spain, July), 338-347
-
(1995)
ICS-95: ACM International Conference on Supercomputing
, pp. 338-347
-
-
Gonzalez, A.1
Aliagas, C.2
Valero, M.3
-
24
-
-
3042601599
-
Access pattern based local memory customization for low-power embedded systems
-
(Munich, Germany, March)
-
Grun, P., Dutt, N., and Nicolau, A. 2001. Access pattern based local memory customization for low-power embedded systems. In DATE-01: IEEE Design Automation and Test in Europe (Munich, Germany, March), 778-784
-
(2001)
DATE-01: IEEE Design Automation and Test in Europe
, pp. 778-784
-
-
Grun, P.1
Dutt, N.2
Nicolau, A.3
-
25
-
-
85025401794
-
Developing a design methodology for embedded memories
-
(Jan.)
-
Hall, E. and Costakis, G. 2001. Developing a design methodology for embedded memories. ISD Mag. (Jan.)
-
(2001)
ISD Mag.
-
-
Hall, E.1
Costakis, G.2
-
26
-
-
0026259617
-
Dual-regulator dual-decoding-trimmer DRAM voltage limiter for burn-in tests
-
Horiguchi, M., et al. 1991. Dual-regulator dual-decoding-trimmer DRAM voltage limiter for burn-in tests. IEEE J. Solid-State Circuits 26, 11, 1544-1549
-
(1991)
IEEE J. Solid-State Circuits
, vol.26
, Issue.11
, pp. 1544-1549
-
-
Horiguchi, M.1
-
27
-
-
21044436759
-
A power reduction technique with object code merging for application specific embedded processors
-
(Paris, France, Mar.)
-
Ishihara, T. and Yasuura, H. 2000. A power reduction technique with object code merging for application specific embedded processors. In DATE'00: Design Automation and Test in Europe (Paris, France, Mar.), 617-623
-
(2000)
DATE'00: Design Automation and Test in Europe
, pp. 617-623
-
-
Ishihara, T.1
Yasuura, H.2
-
28
-
-
0025449455
-
Trends in megabit DRAM circuit design
-
Itoh, K. 1990. Trends in megabit DRAM circuit design. IEEE J. Solid-State Circuits 25, 778-789
-
(1990)
IEEE J. Solid-State Circuits
, vol.25
, pp. 778-789
-
-
Itoh, K.1
-
29
-
-
0029288557
-
Trends in low-power RAM circuit technologies
-
Itoh, K., Sasaki, K., and Nakagome, Y. 1995. Trends in low-power RAM circuit technologies. Proc. IEEE 83, 4, 524-543
-
(1995)
Proc. IEEE
, vol.83
, Issue.4
, pp. 524-543
-
-
Itoh, K.1
Sasaki, K.2
Nakagome, Y.3
-
30
-
-
0031353109
-
Design and performance evaluation of a cache assist to implement selective caching
-
(Austin, TX, Oct.)
-
John, L. K. and Subramanian, A. 1997. Design and performance evaluation of a cache assist to implement selective caching. In ICCD-97: IEEE International Conference on Computer Design (Austin, TX, Oct.), 510-518
-
(1997)
ICCD-97: IEEE International Conference on Computer Design
, pp. 510-518
-
-
John, L.K.1
Subramanian, A.2
-
31
-
-
0025429331
-
Improving direct-mapped cache performance by the addition of a small fully-associative cache and pre-fetch buffer
-
(Seattle, WA, May)
-
Jouppi, N. 1990. Improving direct-mapped cache performance by the addition of a small fully-associative cache and pre-fetch buffer. In ISCA-90: ACM/IEEE International Symposium on Computer Architecture (Seattle, WA, May), 364-373
-
(1990)
ISCA-90: ACM/IEEE International Symposium on Computer Architecture
, pp. 364-373
-
-
Jouppi, N.1
-
32
-
-
0030649425
-
Reducing TLB power requirements
-
(Monterey, CA, Aug.
-
Juan, T., Lang, T., Navarro, J. J. 1997. Reducing TLB power requirements. In ISLPED-97: ACM/IEEE International Symposium on Low Power Electronics and Design (Monterey, CA, Aug.) 196-201
-
(1997)
ISLPED-97: ACM/IEEE International Symposium on Low Power Electronics and Design
, pp. 196-201
-
-
Juan, T.1
Lang, T.2
Navarro, J.J.3
-
33
-
-
0030684367
-
Analytical energy dissipation models for low-power caches
-
(Monterey, CA, Aug.)
-
Kamble, M. B. and Ghose, K. 1997. Analytical energy dissipation models for low-power caches. In ISLPED-97: ACM/IEEE International Symposium on Low Power Electronics and Design (Monterey, CA, Aug.), 143-148
-
(1997)
ISLPED-97: ACM/IEEE International Symposium on Low Power Electronics and Design
, pp. 143-148
-
-
Kamble, M.B.1
Ghose, K.2
-
34
-
-
0035339227
-
Embedded DRAM development: Technology, physical design and application issues
-
Keitel-Schulz, D. and Wehn, N. 2001. Embedded DRAM development: Technology, physical design and application issues. IEEE Des. Test Comput. 18, 3, 7-15
-
(2001)
IEEE Des. Test Comput.
, vol.18
, Issue.3
, pp. 7-15
-
-
Keitel-Schulz, D.1
Wehn, N.2
-
35
-
-
0022733598
-
Power reduction technique in megabit DRAM's
-
Kimura, K., et al. 1986. Power reduction technique in megabit DRAM's. IEEE J. Solid-State Circuits 21, 381-389
-
(1986)
IEEE J. Solid-State Circuits
, vol.21
, pp. 381-389
-
-
Kimura, K.1
-
36
-
-
0031336708
-
The filter cache: An energy efficient memory structure
-
(Research Triangle Park, NC, Dec.
-
Kin, J., Gupta, M., and Mangione-Smith, W. 1997. The filter cache: An energy efficient memory structure. In MICRO-30: Annual IEEE/ACM International Symposium on Microarchitecture (Research Triangle Park, NC, Dec.) 184-193
-
(1997)
MICRO-30: Annual IEEE/ACM International Symposium on Microarchitecture
, pp. 184-193
-
-
Kin, J.1
Gupta, M.2
Mangione-Smith, W.3
-
37
-
-
0032097825
-
Energy optimization of multilevel cache architectures for RISC and CISC processors
-
(June)
-
Ko, U., Balsaha, P. T., and Nanda, A. K. 1998. Energy optimization of multilevel cache architectures for RISC and CISC processors. IEEE Trans. VLSI Syst. 6, 2 (June), 299-308
-
(1998)
IEEE Trans. VLSI Syst.
, vol.6
, pp. 299-308
-
-
Ko, U.1
Balsaha, P.T.2
Nanda, A.K.3
-
38
-
-
12944288247
-
Vector unit architecture for emotion synthesis
-
Kunimatsu, A., et al. 2000. Vector unit architecture for emotion synthesis. IEEE Micro 20, 2, 40-47
-
IEEE Micro
, vol.20
, Issue.2
, pp. 40-47
-
-
Kunimatsu, A.1
-
40
-
-
0034592592
-
Region-based baching: An energy-delay efficient memory architecture for embedded processors
-
Architecture and Synthesis for Embedded Systems (Nov.)
-
Lee, H. S. and Tyson, G. S. 2000. Region-based baching: An energy-delay efficient memory architecture for embedded processors. In IEEE International Conference on Compilers, Architecture and Synthesis for Embedded Systems (Nov.), 120-127
-
(2000)
IEEE International Conference on Compilers
, pp. 120-127
-
-
Lee, H.S.1
Tyson, G.S.2
-
41
-
-
0033701360
-
Code compression for low power embedded systems
-
(Los Angeles, CA, June)
-
Lekatsas, H. and Wolf, W. 2000. Code compression for low power embedded systems. In DAC-37: ACM/IEEE Design Automation Conference (Los Angeles, CA, June), 294-299
-
(2000)
DAC-37: ACM/IEEE Design Automation Conference
, pp. 294-299
-
-
Lekatsas, H.1
Wolf, W.2
-
42
-
-
0032119586
-
Code density optimization for embedded DSP processors using data compression techniques
-
(July)
-
Liao, S. Y., Devadas, S., and Keutzeh, K. 1998. Code density optimization for embedded DSP processors using data compression techniques. IEEE Trans. CAD/ICAS 17, 7 (July), 601-608
-
(1998)
IEEE Trans. CAD/ICAS
, vol.17
, pp. 601-608
-
-
Liao, S.Y.1
Devadas, S.2
Keutzeh, K.3
-
43
-
-
0021476780
-
Half-VDD bit line sensing scheme in CMOS DRAM
-
Lu, N. C. C. and Chao, H. 1984. Half-VDD bit line sensing scheme in CMOS DRAM. IEEE J. Solid-State Circuits 19, 451-454
-
(1984)
IEEE J. Solid-State Circuits
, vol.19
, pp. 451-454
-
-
Lu, N.C.C.1
Chao, H.2
-
44
-
-
0032202489
-
Low-power SHAM design usig half-swing pulse-mode techniques
-
Mai, K., Mohi, T., Amhutuh, B., Ho, H., Wilbuhn, B., and Horowitz, M. 1998. Low-power SHAM design usig half-swing pulse-mode techniques. IEEE J. Solid-State Circuits 33, 1659-1671
-
(1998)
IEEE J. Solid-State Circuits
, vol.33
, pp. 1659-1671
-
-
Mai, K.1
Mohi, T.2
Amhutuh, B.3
Ho, H.4
Wilbuhn, B.5
Horowitz, M.6
-
45
-
-
0010360219
-
The split temporal/spatial cache: A complexity analysis
-
(Santa Clara, CA, Sept.)
-
Milutinovic, V., Mahkovic, B., Tomasevic, M., and Themblay, M. 1996. The split temporal/spatial cache: A complexity analysis. In SCIzzL-6 Workshop (Santa Clara, CA, Sept.), 89-96
-
(1996)
SCIzzL-6 Workshop
, pp. 89-96
-
-
Milutinovic, V.1
Mahkovic, B.2
Tomasevic, M.3
Themblay, M.4
-
46
-
-
84936904234
-
A 20ns 64K CMOS HAM
-
(Feb.)
-
Minato, O., et al. 1984. A 20ns 64K CMOS HAM. ISSCC Dig. Tech. Papers (Feb.), 222-223
-
(1984)
ISSCC Dig. Tech. Papers
, pp. 222-223
-
-
Minato, O.1
-
47
-
-
0343026457
-
Random-access data storage components in customized architectures
-
Nachtergaele, L., Catthoor, F., and Kulkarni, C. 2001. Random-access data storage components in customized architectures. IEEE Des. Test Comput. 18, 3, 40-54
-
(2001)
IEEE Des. Test Comput.
, vol.18
, Issue.3
, pp. 40-54
-
-
Nachtergaele, L.1
Catthoor, F.2
Kulkarni, C.3
-
48
-
-
0031644049
-
A novel, high density, low voltage SRAM cell with a vertical NDR device
-
Nemati, F. and Plummer, J. 1998. A novel, high density, low voltage SRAM cell with a vertical NDR device. In IEEE Symposium on VLSI Technology, 66-67
-
(1998)
IEEE Symposium on VLSI Technology
, pp. 66-67
-
-
Nemati, F.1
Plummer, J.2
-
49
-
-
33746967016
-
Data and memory optimization techniques for embedded systems
-
(April)
-
Panda, P. H., Catthor, F., Dutt, N. D., Danckaert, K., Brockmeyer, E., Kulkarni, C., Vandercappele, A., and Kjeldsberg, P. G. 2001. Data and memory optimization techniques for embedded systems. ACM Trans. Des. Autom. Electron. Syst. 6, 2 (April), 149-206
-
(2001)
ACM Trans. Des. Autom. Electron. Syst.
, vol.6
, pp. 149-206
-
-
Panda, P.H.1
Catthor, F.2
Dutt, N.D.3
Danckaert, K.4
Brockmeyer, E.5
Kulkarni, C.6
Vandercappele, A.7
Kjeldsberg, P.G.8
-
51
-
-
23044524059
-
The data partitioning problem in embedded processor-based systems
-
ACM Trans. Des. Autom. Electron. Syst. (July)
-
Panda, P., Dutt, N., and Nicolau, A. 2001. On-chip vs. off-chip memory: The data partitioning problem in embedded processor-based systems. ACM Trans. Des. Autom. Electron. Syst. 5, 3, (July), 682-704
-
(2001)
On-chip vs. off-chip memory
, vol.5
, pp. 682-704
-
-
Panda, P.1
Dutt, N.2
Nicolau, A.3
-
53
-
-
0035242947
-
Reducing leakage in a high-performance deep-submicron instruction cache
-
(Feb.)
-
Powell, M., Yang, S. H., Falsafi, B., Hou, K., and Vijaykumar, N. 2001. Reducing leakage in a high-performance deep-submicron instruction cache. IEEE Trans. VLSI Syst. 9, 1 (Feb.), 77-89
-
(2001)
IEEE Trans. VLSI Syst.
, vol.9
, pp. 77-89
-
-
Powell, M.1
Yang, S.H.2
Falsafi, B.3
Hou, K.4
Vijaykumar, N.5
-
54
-
-
0035339148
-
Design and test of large embedded memories: An overview
-
Hajsuman, H. 2001. Design and test of large embedded memories: An overview. IEEE Des. Test Comput. 18, 3, 16-27
-
(2001)
IEEE Des. Test Comput.
, vol.18
, Issue.3
, pp. 16-27
-
-
Hajsuman, H.1
-
55
-
-
0021475239
-
Fault-tolerant semiconductor memories
-
Sarhazin, D. and Malek, M. 1984. Fault-tolerant semiconductor memories. IEEE Comput. 17, 8, 49-56
-
(1984)
IEEE Comput.
, vol.17
, Issue.8
, pp. 49-56
-
-
Sarhazin, D.1
Malek, M.2
-
56
-
-
0024751720
-
A 9-ns 1-Mbit CMOS HAM
-
Sasaki, K., et al. 1989. A 9-ns 1-Mbit CMOS HAM. IEEE J. Solid-State Circuits 24, 1219-1225
-
(1989)
IEEE J. Solid-State Circuits
, vol.24
, pp. 1219-1225
-
-
Sasaki, K.1
-
57
-
-
0035687345
-
Memory built-in self-repair using redundant words
-
Schober, V., Paul, S., and Picot, O. 2001. Memory built-in self-repair using redundant words. In International Test Conference, 995-1001
-
(2001)
International Test Conference
, pp. 995-1001
-
-
Schober, V.1
Paul, S.2
Picot, O.3
-
59
-
-
0004159678
-
Memory exploration for low power, embedded systems
-
(New Orleans, LA, June)
-
Shiue, W. and Chakrabarti, C. 1999. Memory exploration for low power, embedded systems. In DAC-36: ACM/IEEE Design Automation Conference (New Orleans, LA, June), 140145
-
(1999)
DAC-36: ACM/IEEE Design Automation Conference
, pp. 140145
-
-
Shiue, W.1
Chakrabarti, C.2
-
60
-
-
0034431747
-
Overview of radiation tolerant unlimited write cycle non-volatile memory
-
(Mar)
-
Strauss, K. and Daud, T. 2000. Overview of radiation tolerant unlimited write cycle non-volatile memory. In IEEE Aereospace Conference (Mar), 399-408
-
(2000)
IEEE Aereospace Conference
, pp. 399-408
-
-
Strauss, K.1
Daud, T.2
-
61
-
-
0029192697
-
Cache design trade-offs for power and performance optimization: A case study
-
(Dana Point, CA, Apr.)
-
Su, C. L. and Despain, A. M. 1995. Cache design trade-offs for power and performance optimization: A case study. In ISLPD-95: ACM/IEEE International Symposium on Low Power Design (Dana Point, CA, Apr.), 63-68
-
(1995)
ISLPD-95: ACM/IEEE International Symposium on Low Power Design
, pp. 63-68
-
-
Su, C.L.1
Despain, A.M.2
-
62
-
-
18344409970
-
A microprocessor with a 128-bit CPU, ten floating-point MACs, four floating-point dividers and an MPEG-2 decoder
-
Suzuoki, M., et al. 1999. A microprocessor with a 128-bit CPU, ten floating-point MACs, four floating-point dividers and an MPEG-2 decoder. IEEE J. Solid-State Circuits 34, 11, 1608-1618
-
(1999)
IEEE J. Solid-State Circuits
, vol.34
, Issue.11
, pp. 1608-1618
-
-
Suzuoki, M.1
-
63
-
-
0034316132
-
A 60-MHz 240-mW MPEG-4 videophone LSI with 16-Mb embedded DRAM
-
Takahashi, M., et al. 2000. A 60-MHz 240-mW MPEG-4 videophone LSI with 16-Mb embedded DRAM. IEEE J. Solid-State Circuits 35, 11, 1713-1721
-
(2000)
IEEE J. Solid-State Circuits
, vol.35
, Issue.11
, pp. 1713-1721
-
-
Takahashi, M.1
-
64
-
-
0035498767
-
Ferroelectric memories and their applications
-
Takasu, H. 2001. Ferroelectric memories and their applications. Microelectron. Eng. 59, 237-246
-
(2001)
Microelectron. Eng.
, vol.59
, pp. 237-246
-
-
Takasu, H.1
-
65
-
-
0344507617
-
Stabilization of voltage limiter circuit for high-density DRAM's using pole-zero compensation
-
(Nov.)
-
Tanaka, H., et al. 1992. Stabilization of voltage limiter circuit for high-density DRAM's using pole-zero compensation. IEICE Trans. Electron. E75-C, 1 (Nov.), 1333-1343
-
(1992)
IEICE Trans. Electron.
, vol.E75-C
, Issue.1
, pp. 1333-1343
-
-
Tanaka, H.1
-
66
-
-
1642306627
-
Power savings in embedded processors through decode file cache
-
(Paris, France, Mar.)
-
Tang, W., Gupta, R., and Nicolau, A. 2002. Power savings in embedded processors through decode file cache. In DATE'02: Design and Test in Europe (Paris, France, Mar.), 443-448
-
(2002)
DATE'02: Design and Test in Europe
, pp. 443-448
-
-
Tang, W.1
Gupta, R.2
Nicolau, A.3
-
67
-
-
0033711828
-
Low-power technique for on-chip memory using biased partitioning and access concentration
-
(May)
-
Usami, K. and Kawabe, N. 2000. Low-power technique for on-chip memory using biased partitioning and access concentration. In IEEE Custom Integrated Circuits Conference (May), 214-220
-
(2000)
IEEE Custom Integrated Circuits Conference
, pp. 214-220
-
-
Usami, K.1
Kawabe, N.2
-
68
-
-
0029500701
-
Pollution control caching
-
(Austin, TX, Oct.)
-
Walsh, S. J. and Board, J. A. 1995. Pollution control caching. In ICCD-95: IEEE International Conference on Computer Design (Austin, TX, Oct.), 300-306
-
(1995)
ICCD-95: IEEE International Conference on Computer Design
, pp. 300-306
-
-
Walsh, S.J.1
Board, J.A.2
-
69
-
-
0031370567
-
Low-power and high-speed advantages of DRAM-logic integration for multimedia systems
-
Watanabe, T., Fujita, R., and Yanagisawa, K. 1997. Low-power and high-speed advantages of DRAM-logic integration for multimedia systems. IECE Trans. Electron. E80-C, 12, 1523-1531
-
(1997)
IECE Trans. Electron.
, vol.E80-C
, Issue.12
, pp. 1523-1531
-
-
Watanabe, T.1
Fujita, R.2
Yanagisawa, K.3
-
70
-
-
0034224349
-
On the go with SONOS
-
White, M., Adams, D., and Bu, J. 2000. On the go with SONOS. IEEE Circuits Devices 16, 4, 22-31
-
(2000)
IEEE Circuits Devices
, vol.16
, Issue.4
, pp. 22-31
-
-
White, M.1
Adams, D.2
Bu, J.3
-
71
-
-
0034462656
-
Frequent value compression in data caches
-
(Monterey, CA, Dec.)
-
Yang, J., Zhang, Y., and Gupta, R. 2000. Frequent value compression in data caches. In MICRO-33: IEEE/ACM 33d International Symposium on Microarchitecture (Monterey, CA, Dec.), 258-265
-
(2000)
MICRO-33: IEEE/ACM 33d International Symposium on Microarchitecture
, pp. 258-265
-
-
Yang, J.1
Zhang, Y.2
Gupta, R.3
-
72
-
-
0030650199
-
An object code compression approach to embedded processors.
-
(Monterey, CA, Aug.)
-
Yoshida, Y., Song, B., Okuhata, H., Onoye, T., and Shirakawa, I. 1997. An object code compression approach to embedded processors. In ISLPED-97: ACM/IEEE International Symposium on Low Power Electronics and Design. (Monterey, CA, Aug.), 265-268
-
(1997)
ISLPED-97: ACM/IEEE International Symposium on Low Power Electronics and Design.
, pp. 265-268
-
-
Yoshida, Y.1
Song, B.2
Okuhata, H.3
Onoye, T.4
Shirakawa, I.5
-
73
-
-
77956830995
-
Yield improvement and repair trade-off for large embedded memories
-
Zorian, Y. 2000. Yield improvement and repair trade-off for large embedded memories. IEEE Des. Test Eur. 69-70
-
(2000)
IEEE Des. Test Eur
, pp. 69-70
-
-
Zorian, Y.1
|