A 500 fW/bit 14 fJ/bit-access 4kb standard-cell based sub-VT memory in 65nm CMOS

European Solid-State Circuits Conference

Volumn , Issue , 2012, Pages 321-324

  Meinerzhagen, Pascal ^a   Andersson, Oskar ^b   Mohammadi, Babak ^b   Sherazi, Yasser ^b   Burg, Andreas ^a   Rodrigues, Joachim Neves ^b  

^a EPFL   (Switzerland)

^b LUND UNIVERSITY   (Sweden)

Author keywords

[No Author keywords available]

Indexed keywords

65NM CMOS TECHNOLOGY; BIOMEDICAL IMPLANTS; D-LATCH; DATA-RETENTION; LEAKAGE POWER; MEMORY COMPILERS; OUTPUT BUFFER; STANDARD-CELL; STORAGE ARRAYS; SUBTHRESHOLD; TOTAL ENERGY; ULTRA-LOW POWER;

CMOS INTEGRATED CIRCUITS; SENSOR NODES;

DIGITAL STORAGE;

EID: 84870809271     PISSN: 19308833     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ESSCIRC.2012.6341319     Document Type: Conference Paper

References (9)

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