Reducing datapath energy through the isolation of short-lived operands

Parallel Architectures and Compilation Techniques - Conference Proceedings, PACT

Volumn 2003-January, Issue , 2003, Pages 258-268

  Ponomarev, D ^a   Kucuk, G ^a   Ergin, O ^a   Ghose, K ^a  

^a State University of New York at Binghamton   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

ARCHITECTURE; CMOS INTEGRATED CIRCUITS;

ARCHITECTURAL REGISTER FILES; BRANCH MISPREDICTIONS; CMOS PROCESSS; ENERGY REDUCTION; MEASUREMENTS OF; PHYSICAL REGISTERS; RE-ORDER BUFFERS; REGISTER FILES;

PARALLEL ARCHITECTURES;

EID: 84968806856     PISSN: 1089795X     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/PACT.2003.1238021     Document Type: Conference Paper

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