Reducing reorder buffer complexity through selective operand caching

Proceedings of the International Symposium on Low Power Electronics and Design

Volumn 2003-January, Issue , 2003, Pages 235-240

  Kucuk, G ^a   Ponomarev, D T ^a   Ergin, O ^a   Ghose, K ^a  

^a State University of New York at Binghamton   (United States)

Author keywords

Algorithm design and analysis; Computer science; Degradation; Microarchitecture; Microprocessors; Out of order; Permission; Pipelines; Power dissipation; Registers

Indexed keywords

COMPUTER ARCHITECTURE; COMPUTER SCIENCE; DEGRADATION; DESIGN; ENERGY DISSIPATION; LOW POWER ELECTRONICS; MICROPROCESSOR CHIPS; PIPELINES; POWER ELECTRONICS; RECORDING INSTRUMENTS;

ALGORITHM DESIGN AND ANALYSIS; MICRO ARCHITECTURES; OUT OF ORDER; PERMISSION; REGISTERS;

ELECTRIC LOSSES;

EID: 1542359146     PISSN: 15334678     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/LPE.2003.1231868     Document Type: Conference Paper

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