Efficient test data decompression for system-on-a-chip using an embedded FPGA core

Proceedings - IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems

Volumn 2003-January, Issue , 2003, Pages 503-510

  Zeng, Gang ^a   Ito, Hideo ^a  

^a CHIBA UNIVERSITY   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

APPLICATION SPECIFIC INTEGRATED CIRCUITS; ASSOCIATIVE STORAGE; COMPUTER HARDWARE; DATA COMPRESSION; DEFECTS; DESIGN FOR TESTABILITY; EMBEDDED SYSTEMS; FAULT TOLERANCE; FIELD PROGRAMMABLE GATE ARRAYS (FPGA); HARDWARE; INTEGRATED CIRCUIT TESTING; MEMORY ARCHITECTURE; PROGRAMMABLE LOGIC CONTROLLERS; RECONFIGURABLE HARDWARE;

EMBEDDED PROCESSORS; HARDWARE OVERHEADS; HIGH POWER CONSUMPTION; HUFFMAN CODING; RECONFIGURABLE; SYSTEM ON A CHIP; TEST APPLICATION TIME; TEST-DATA VOLUME;

SYSTEM-ON-CHIP;

EID: 84964928681     PISSN: 15505774     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/TSM.2005.1250149     Document Type: Conference Paper

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