Corrections to: Interconnect design and benchmarking for charge-based beyond-CMOS device proposals (IEEE Electron Device Letters (2016) 37:4 (508-511) DOI: 10.1109/LED.2016.2532350);Interconnect design and benchmarking for charge-based beyond-CMOS device proposals

IEEE Electron Device Letters

Volumn 37, Issue 4, 2016, Pages 508-511

  Pan, Chenyun ^a   Naeemi, Azad ^a  

^a GEORGIA INSTITUTE OF TECHNOLOGY   (United States)

Author keywords

Beyond CMOS technology; Interconnect; Repeater; Span of control

Indexed keywords

CMOS INTEGRATED CIRCUITS; ECONOMIC AND SOCIAL EFFECTS; INTEGRATED CIRCUIT DESIGN; TELECOMMUNICATION REPEATERS;

BEYOND CMOS; CHARGE BASED DEVICES; GRAPHENE P-N JUNCTIONS; INTERCONNECT; INTERCONNECT DESIGN; INTERCONNECT PERFORMANCE; INTRINSIC DEVICE; SPAN-OF-CONTROL;

INTEGRATED CIRCUIT INTERCONNECTS;

EID: 84963807296     PISSN: 07413106     EISSN: None     Source Type: Journal    
DOI: 10.1109/LED.2017.2687862     Document Type: Erratum

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