Device- and system-level performance modeling for graphene P-N junction logic

Proceedings - International Symposium on Quality Electronic Design, ISQED

Volumn , Issue , 2012, Pages 262-269

  Pan, Chenyun ^a   Naeemi, Azad ^a  

^a GEORGIA INSTITUTE OF TECHNOLOGY   (United States)

Author keywords

Graphene PN junction; resistance and capacitance model; system level performance evaluation; transmission probability

Indexed keywords

CAPACITANCE MODEL; CMOS CIRCUITS; CMOS LOGIC CIRCUITS; CU/LOW-K INTERCONNECTS; DIE SIZE; LEAKAGE RESISTANCE; LOGIC SYSTEMS; MUX-BASED; ON-RESISTANCE; OUTPUT RESISTANCE; P-N JUNCTION; POWER DENSITIES; RESISTANCE MODELS; SI CMOS; SYSTEM-LEVEL ANALYSIS; SYSTEM-LEVEL PERFORMANCE; TECHNOLOGY NODES; TRANSMISSION PROBABILITIES;

CMOS INTEGRATED CIRCUITS; ELECTRIC RESISTANCE; LOGIC CIRCUITS; LOGIC DEVICES; SEMICONDUCTOR JUNCTIONS; SILICON;

GRAPHENE;

EID: 84863648919     PISSN: 19483287     EISSN: 19483295     Source Type: Conference Proceeding    
DOI: 10.1109/ISQED.2012.6187504     Document Type: Conference Paper

References (17)

1. F. Schwierz, "Graphene transistors" Nature Nanotech., vol. 5, 487, 2010.
2. Katsnelson, M. I., Novoselov, K. S. and Geim, A. K, "Chiral tunnelling and the Klein paradox in graphene,"Nature Phys. 2, pp. 620-625, 2006. (Pubitemid 44328348)
3. S. Tanachutiwat, J. U. Lee, W. Wang, and C. Y. Sung, "Reconfigurable multi-function logic based on graphene p-n junctions," in Design Automation Conference, DAC. ACM, pp. 883-888, 2010.
4. G. A. Sai-Halaz, "Performance trends in high-end processors," Proc. IEEE, vol. 83, pp. 20-36, Jan. 1995.
5. D. C. Sekar, A. Naeemi, R. Sarvari, J. A. Davis, and J. D. Meindl, "IntSim: A CAD tool for Optimization of Multi-level Interconnect Networks," in Proc. IEEE Int. Conf. on Computer-Aided Design, 2007.
6. V. V. Cheianov et al., "Selective transmission of Dirac electrons and ballistic magnetoresistance of n-p junctions in graphene," Phys. Rev. B, vol. 74, p. 041403(R), 2006.
7. S. Datta, Quantum Transport: Atom to Transistor, Cambridge, U.K.: Cambridge Univ. Press, 2005.
8. A. Das et al., "Phonon renormalization in doped bilayer graphene," Phys. Rev. B, vol. 79, p. 155417, 2009.
9. Low, T., and J. Appenzeller, "Electronic transport properties of a tilted graphene p-n junction," Phys. Rev. B 80 (15), 155406, 2009.
10. R. N. Sajjad, and A.V. Ghosh, "High efficiency switching using graphene based electron 'optics'," arXiv:1107.2383, 2011.
11. S. Datta, Electronic Transport in Mesoscopic Systems, Cambridge, U.K.: Cambridge Univ. Press, 1995.
12. F. Xia, V. Perebeinos, Y.-M. Lin, Y. Wu, and P. Avouris, "The Origins and Limits of Metal-Graphene Junction Resistance," Nature Nano 6, pp. 179-184, 2011.
13. RAPHAEL: Interconnect Analysis Program, TMA Inc, 1996
14. International Technology Roadmap for Semiconductors (ITRS), 2010 ed.: Semiconductor Industry Assoc., 2010.
15. R. Venkatesan, J. Davis, et al., "Optimal n tier multilevel interconnect architectures for GSI," Trans. VLSI Systems, Dec 2001.
16. V. Kumar, S. Rakheja, and A. Naeemi, "Modeling and optimization for multi-layer graphene nanoribbon conductors," in Proc. IEEE Int. Interconnect Technol. Conf., May 9-12, 2011, pp. 1-3.
17. Y. Sui and J. Appenzeller, "Screening and Interlayer Coupling in Multilayer Graphene Field-Effect Transistors," J. Nano Letters, 9, (2009), 2973-2977