Constraint driven pin mapping for concurrent SOC testing

Proceedings - 7th Asia and South Pacific Design Automation Conference, 15th International Conference on VLSI Design, ASP-DAC/VLSI Design 2002

Volumn , Issue , 2002, Pages 511-516

  Huang, Yu ^a   Mukherjee, Nilanjan ^b   Tsai, Chien Chung ^b   Samman, O ^b   Zaidan, Yahya ^b   Zhang, Yanping ^b   Cheng, Wu Tung ^b   Reddy, S M ^a  

^a IA United States   (United States)

^b MENTOR GRAPHICS CORPORATION   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

APPLICATION SPECIFIC INTEGRATED CIRCUITS; COMPUTATIONAL COMPLEXITY; COMPUTER AIDED DESIGN; HEURISTIC ALGORITHMS; MAPPING; PROGRAMMABLE LOGIC CONTROLLERS; SYSTEM-ON-CHIP;

CONCURRENT TEST; CORE-BASED DESIGN; COST-EFFICIENT; SOC TESTING; SYSTEM ON A CHIP;

DESIGN;

EID: 84962249208     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ASPDAC.2002.994971     Document Type: Conference Paper

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