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Volumn 2002-January, Issue , 2002, Pages 21-27

A power model for routers: Modeling Alpha 21364 and InfiniBand routers

Author keywords

Blades; Communication switching; Energy consumption; Fabrics; IP networks; Microprocessors; Multiprocessor interconnection networks; Network servers; Network on a chip; Switches

Indexed keywords

COMPUTER ARCHITECTURE; ECONOMIC AND SOCIAL EFFECTS; ENERGY UTILIZATION; FABRICS; INTEGRATED CIRCUIT INTERCONNECTS; INTERCONNECTION NETWORKS (CIRCUIT SWITCHING); MICROPROCESSOR CHIPS; QUEUEING NETWORKS; SWITCHES;

EID: 21044439794     PISSN: 15504794     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/CONECT.2002.1039253     Document Type: Conference Paper
Times cited : (39)

References (23)
  • 15
    • 85008055290 scopus 로고    scopus 로고
    • Power-efficient interconnection networks: Dynamic voltage scaling with links
    • L. Shang, L.-S. Peh, and N. K. Jha. Power-efficient interconnection networks: Dynamic voltage scaling with links. Computer Architecture Letters, 1(2), 2002
    • (2002) Computer Architecture Letters , vol.1 , Issue.2
    • Shang, L.1    Peh, L.-S.2    Jha, N.K.3
  • 16
    • 16244422284 scopus 로고    scopus 로고
    • Synopsys Corporation
    • Synopsys Corporation. PowerMill datasheet. http://www.synopsys.com/products/etg/powermillds.html
    • PowerMill Datasheet
  • 18
    • 0003650381 scopus 로고
    • An enhanced access and cycle time model for on-chip caches
    • DEC Western Research Laboratory
    • S. J. Wilton and N. P. Jouppi. An enhanced access and cycle time model for on-chip caches. Technical Report 93/5, DEC Western Research Laboratory, 1994
    • (1994) Technical Report , vol.93 , Issue.5
    • Wilton, S.J.1    Jouppi, N.P.2


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.