Double gate tunnel FET with ultrathin silicon body and high-k gate dielectric

ESSDERC 2006 - Proceedings of the 36th European Solid-State Device Research Conference

Volumn , Issue , 2006, Pages 383-386

  Boucart, Kathy ^a   Ionescu, Adrian Mihai ^a  

^a EPFL   (Switzerland)

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTER SIMULATION; DIELECTRIC DEVICES; ELECTRIC CURRENTS; SILICON;

DOUBLE GATE TUNNEL FIELD EFFECT TRANSISTOR (DG TFET); ON-CURRENT; SUBTHRESHOLD SWING;

FIELD EFFECT TRANSISTORS;

EID: 84943200515     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ESSDER.2006.307718     Document Type: Conference Paper

References (15)

1. W. Reddick and G. Amaratunga, "Silicon surface tunnel transistor," Appl. Phys. Lett., vol. 67, no. 4, 1995, pp. 494-496.
2. J. Koga and A. Toriumi, "Three-Terminal Silicon Surface Junction Tunneling Device for Room Temperature Operation," IEEE Elec. Dev. Lett., vol. 20, no. 10, 1999, pp. 529-531.
3. W. Hansch, C. Fink, J. Schulze, and I. Eisele, "A vertical MOS-gated Esaki tunneling transistor in silicon," Thin Solid Films, vol. 369, 2000, pp. 387-389.
4. C. Aydin, et al., "Lateral interband tunneling transistor in silicon-on-insulator," Appl. Phys. Lett., vol. 84, no. 10, 2004, pp. 1780-1782.
5. J. Appenzeller, Y.-M. Lin, J. Knoch, and Ph. Avouris, "Band-to-Band Tunneling in Carbon Nanotube Field-Effect Transistors," Phys. Rev. Lett., vol. 93, no. 19, 2004, pp. 196805-1-4.
6. P.-F. Wang, et al., "Complementary tunneling transistor for low power application," Solid-State Elec., vol. 48, 2004, pp. 2281-2286.
7. K. Bhuwalka, S. Sedimaier, A. Ludsteck, C. Tolksdorf, J. Schulze, and I. Eisele, "Vertical Tunnel Field-Effect Transistor," IEEE Trans. Elec. Dev., vol. 51, no. 2, 2004, pp. 279-282.
8. K. Bhuwalka, J. Schulze, and I. Eisele, "A Simulation Approach to Optimize the Electrical Parameters of a Vertical Tunnel FET," IEEE Trans. Elec. Dev., vol. 52, no. 7, 2005, pp. 1541-1547.
9. K. Bhuwalka, J. Schulze, and I. Eisele, "Performance Enhancement of Vertical Tunnel Field-Effect Transistor with SiGe in the delta p+ Layer," Jap. J. Appl. Phys., vol. 43, no. 7A, 2004, pp. 4073-4078.
10. Th. Nirschl, et al., "The Tunneling Field Effect Transistor (TFET) as an Add-on for Ultra-Low-Voltage Analog and Digital Processes," IEDM, Technical Digest of, 2004, pp. 8.3.1-4.
11. Q. Zhang, W. Zhao, and A. Seabaugh, "Analytic Expression and Approach for Low Subthreshold-Swing Tunnel Transistors," Device Research Conference (DRC), June 20-22, 2005, Santa Barbara, CA.
12. ITRS Roadmap, 2005, available online at http://www.itrs.net.
13. K. Kim and J. Fossum "Double-Gate CMOS: Symmetrical-Versus Asymmetrical-Gate Devices," IEEE Trans. Elec. Dev., vol. 48, no. 2, 2001, pp. 294-299.
14. J. Knoch and J. Appenzeller, DRC '05, 63rd, vol. 1, June 20-22, 2005, pp. 153-156.
15. F. Balestra, S. Cristoloveanu, M. Benachir, J. Brini, and T. Elewa, "Double-gate silicon-on-insulator transistor with volume inversion: a new device with greatly enhanced performance, IEEE Elec. Dev. Lett., vol. 8, no. 9, 1987, pp. 410-412.