A low-power fat tree-based optical network-on-chip for multiprocessor system-on-chip

Proceedings -Design, Automation and Test in Europe, DATE

Volumn , Issue , 2009, Pages 3-8

  Gu, Huaxi ^a   Xu, Jiang ^a   Zhang, Wei ^b  

^a HONG KONG UNIVERSITY OF SCIENCE AND TECHNOLOGY   (Hong Kong)

^b PRINCETON UNIVERSITY   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

APPLICATION SPECIFIC INTEGRATED CIRCUITS; BANDWIDTH; BINARY ALLOYS; ELECTRIC POWER UTILIZATION; FIBER OPTIC NETWORKS; LOW POWER ELECTRONICS; MULTIPROCESSING SYSTEMS; OPTICAL WAVEGUIDES; PACKET SWITCHING; POWER MANAGEMENT (TELECOMMUNICATION); PROGRAMMABLE LOGIC CONTROLLERS; RESONATORS; ROUTERS;

CIRCUIT SWITCHING; COMMUNICATION BANDWIDTH; HIGH PERFORMANCE APPLICATIONS; METALLIC INTERCONNECTS; MULTIPROCESSOR SYSTEM ON CHIPS; NETWORK THROUGHPUT; NETWORKS ON CHIPS; ON CHIP COMMUNICATION;

NETWORK-ON-CHIP;

EID: 84923480914     PISSN: 15301591     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/date.2009.5090624     Document Type: Conference Paper

References (30)

1. L. Benini, G. De Micheli, "Networks on chip: A new paradigm for systems on chip design", Design, Automation and Test in Europe Conference and Exhibition, 2002.
2. M. Sgroi, M. Sheets, A. Mihal, K. Keutzer, S. Malik, J. Rabaey, A. Sangiovanni-Vincentelli, "Addressing the system-on-a-chip interconnect woes through communication-based design", Design Automation Conference, 2001.
3. V. Reyes, T. Bautista, G. Marrero, A. Núñez, W. Kruijtzer, "A multicast inter-task communication protocol for embedded multiprocessor systems," Conference on Hardware-Software Codesign and System Synthesis, 2005: 267-272.
4. W. Dally, B. Towles, "Route packets, not wires: On-chip interconnection networks", Design Automation Conference, 2001.
5. S. Kumar, A. Jantsch, J.P. Soininen, M. Forsell, M. Millberg, J. Öberg, K. Tiensyrjä, and A. Hemani, "A network on chip architecture and design methodology", IEEE Computer Society Annual Symposium on VLSI, 2002.
6. K. Goossens, J. Dielissen, A. Radulescu, "Æthereal network on chip: Concepts, architectures and implementations", IEEE Design Test Comput, Vol.22, No.5, pp414-421. 2005.
7. A. Kumar, L. S. Peh, P. Kundu, N. K. Jha, "Toward Ideal On-Chip Communication Using Express Virtual Channels," IEEE Micro 28(1): 80-90, 2008.
8. M. Amde, T. Felicijan, A. Efthymiou, D. Edwards, and L. Lavagno, "Asynchronous on-chip networks," in IEE Proceedings: Computers and Digital Techniques, 2005, pp. 273-283.
9. J. Xu, W. Wolf, J. Henkel, and S. Chakradhar, "A Design Methodology for Application-Specific Networks-on-Chip", ACM Transactions on Embedded Computing Systems, July 2006.
10. A. Shacham, B.G. Lee, A. Biberman, K. Bergman, L.P. Carloni, "Photonic NoC for DMA Communications in Chip Multiprocessors", Hot Interconnects, 2007.
11. M. Briere, B. Girodias, et al, "System Level Assessment of an Optical NoC in an MPSoC Platform", Design, Automation & Test in Europe Conference & Exhibition, 2007.
12. G. Chen, H. Chen, M. Haurylau, N. A. Nelson, D. H. Albonesi, P. M. Fauchet, and E. G. Friedman, "Predictions of CMOS Compatible On-Chip Optical Interconnect," Integration, the VLSI Journal, Vol. 40, No. 4, pp. 434 - 446, July 2007.
13. A. Shacham, K. Bergman, L. P. Carloni, "The Case for Low-Power Photonic Networks on Chip," in Design Automation Conference 2007, pp. 132-13.
14. F. Xia, L. Sekaric, and Y. Vlasov, "Ultracompact optical buffers on a silicon chip," Nature Photonics, 65-71, 2007.
15. Q. Xu, B. Schmidt, S. Pradhan, M. Lipson, "Micrometre-scale silicon electro-optic modulator", Nature, Vol.435, No.7040, pp325-327, 2005.
16. 2microring resonator optical channel dropping filters," IEEE Photonics Technology Letters, vol. 10, no. 4, pp. 549-551, 1998.
17. A. W. Poon, F. Xu, X. Luo, "Cascaded active silicon microresonator array cross-connect circuits for WDM networks-on-chip", in Proc. SPIE. Vol.6898, 2008.
18. H. Gu, J. Xu, Z. Wang, "ODOR: a Microresonator-based High-performance Low-cost Router for Optical Networks-on-Chip", in Proceedings of International Conference on Hardware-Software Codesign and System Synthesis, 2008.
19. C. E. Leiserson, Z. S. Abuhamdeh, D. C. Douglas, C. R. Feynman, M. N. Ganmukhi, and et al., "The network architecture of the connection machine CM-5," in Proceedings of the fourth annual ACM symposium on Parallel algorithms and architectures, pp. 272-285, 1992.
20. H. Hossain, M. Akbar, and M. Islam, "Extended-butterfly fat tree interconnection (EFTI) architecture for network on chip," in IEEE Pacific Rim Conference on Communications, Computers and signal Processing, 2005, pp. 613-616.
21. Y. L. Jeang, W. H. Huang, and W. F. Fang, "A binary tree architecture for Application Specific Network on Chip (ASNOC) design," in IEEE Asia-Pacific Conference on Circuits and Systems, 2004, pp. 877-880.
22. A. Adriahantenaina, H. Charlery, A. Greiner, L. Mortiez, and C. A. Zeferino, "SPIN: a scalable, packet switched, on-chip micronetwork," in Design, Automation and Test in Europe Conference and Exhibition(DATE), 2003, pp. 70-73.
23. P. P. Pande, C. Grecu, M. Jones, A. Ivanov, and R. Saleh, "Performance evaluation and design trade-offs for network-on-chip interconnect architectures," IEEE Transactions on Computers, vol. 54, pp. 1025-1040, Aug 2005.
24. V. Strumpen and A. Krishnamurthy, "A collision model for randomized routing in fat-tree networks," Journal of Parallel and Distributed Computing, vol. 65, pp. 1007-1021, 2005.
25. J. Kim, C. Nicopoulos, D. Park, R. Das, Yuan Xie, N. Vijaykrishnan, C. Das. "A Novel Dimensionally-Decomposed Router for On-Chip Communication in 3D Architectures." Proceedings of the Annual International Symposium on Computer Architecture (ISCA), pp. 138-149, June 2007.
26. www.si2.org
27. Q. Xu, S. Manipatruni, B. Schmidt, J. Shakya, M. Lipson, "12.5 Gbit/s carrier injection-based silicon microring silicon modulators", Optics Express, Vol.15, No.2, pp430-436, 2007.
28. C. Kromer, G. Sialm, C. Berger, T. Morf, M.L. Schmatz, F. Ellinger, et al.,"A 100-mW 4×10 Gb/s transceiver in 80-nm CMOS for high-density optical interconnects, " IEEE Journal of Solid-State Circuit 40 (2005) (12), pp. 2667-2679.
29. S. Xiao, M. H. Khan, H. Shen, and M. Qi, "Multiple-channel silicon micro-resonator based filters for WDM applications," Optics Express, vol. 15, pp. 7489-7498, 2007.
30. ww.opnet.com