TSP: Thermal safe power - Efficient power budgeting for many-core systems in dark silicon

2014 International Conference on Hardware/Software Codesign and System Synthesis, CODES+ISSS 2014

Volumn , Issue , 2014, Pages

  Pagani, Santiago ^a   Khdr, Heba ^a   Munawar, Waqaas ^a   Chen, Jian Jia ^b   Shafique, Muhammad ^a   Li, Minming ^c   Henkel, Jörg ^a  

^a KARLSRUHE INSTITUTE OF TECHNOLOGY   (Germany)

^b TU DORTMUND UNIVERSITY   (Germany)

^c CITY UNIVERSITY OF HONG KONG   (Hong Kong)

Author keywords

[No Author keywords available]

Indexed keywords

BUDGET CONTROL; HARDWARE-SOFTWARE CODESIGN; SILICON; THERMAL MANAGEMENT (ELECTRONICS);

CHIP MANUFACTURERS; CONSTANT VALUES; COOLING SOLUTIONS; DYNAMIC THERMAL MANAGEMENT; PERFORMANCE LOSS; POWER CONSTRAINTS; SYSTEM DESIGNERS; THERMAL DESIGNS;

TEMPERATURE CONTROL;

EID: 84910646869     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1145/2656075.2656103     Document Type: Conference Paper

References (20)

1. C. Bienia, S. Kumar, J. P. Singh, and K. Li. The PARSEC benchmark suite: Characterization and architectural implications. In PACT, pages 72-81, 2008.
2. N. Binkert, B. Beckmann, and others. The gem5 simulator. SIGARCH Comput. Archit. News, 39(2):1-7, Aug. 2011.
3. H. Bokhari, H. Javaid, M. Shafique, J. Henkel, and S. Parameswaran. darkNoC: Designing energy-efficient network-on-chip with multi-vt cells for dark silicon. In DAC, pages 161:1-161:6, 2014.
4. J. Cebrian, L. Natvig, and J. Meyer. Improving energy efficiency through parallelization and vectorization on intel core i5 and i7 processors. In SC Companion, pages 675-684, 2012.
5. G. Dantzig and M. Thapa. Linear Programming 2: Theory and Extensions. Springer-Verlag, 2003.
6. T. Ebi, D. Kramer, W. Karl, and J. Henkel. Economic learning for thermal-aware power budgeting in many-core architectures. In CODES+ISSS, pages 189-196, 2011.
7. H. Esmaeilzadeh, E. Blem, R. St.Amant, K. Sankaralingam, and D. Burger. Dark silicon and the end of multicore scaling. In ISCA, pages 365-376, 2011.
8. A. Grenat, S. Pant, R. Rachala, and S. Naffiziger. 5.6 adaptive clocking system for improved power efficiency in a 28nm x86-64 microprocessor. In ISSCC, pages 106-107, 2014.
9. W. Huang, S. Ghosh, S. Velusamy, K. Sankaranarayanan, K. Skadron, and M. R. Stan. HotSpot: A compact thermal modeling methodology for early-stage VLSI design. IEEE Transactions on VLSI Systems, 14(5):501-513, May 2006.
10. Intel Corporation. Dual-core intel xeon processor 5100 series datasheet, revision 003, August 2007.
11. F. Kriebel, S. Rehman, D. Sun, M. Shafique, and J. Henkel. ASER: Adaptive soft error resilience for reliability-heterogeneous processors in the dark silicon era. In DAC, pages 12:1-12:6, 2014.
12. E. Kultursay, K. Swaminathan, V. Saripalli, V. Narayanan, M. T. Kandemir, and S. Datta. Performance enhancement under power constraints using heterogeneous CMOS-TFET multicores. In CODES+ISSS, pages 245-254, 2012.
13. J. Lee and N. S. Kim. Optimizing throughput of power- and thermal-constrained multicore processors using DVFS and per-core power-gating. In DAC, pages 47-50, 2009.
14. S. Li, J.-H. Ahn, R. Strong, J. Brockman, D. Tullsen, and N. Jouppi. McPAT: An integrated power, area, and timing modeling framework for multicore and manycore architectures. In MICRO-42, pages 469-480, 2009.
15. T. Muthukaruppan, M. Pricopi, V. Venkataramani, T. Mitra, and S. Vishin. Hierarchical power management for asymmetric multi-core in dark silicon era. In DAC, pages 174:1-174:9, 2013.
16. S. Nussbaum. AMD trinity APU. In Hot Chips, 2012.
17. B. Raghunathan and S. Garg. Job arrival rate aware scheduling for asymmetric multi-core servers in the dark silicon era. In CODES+ISSS, 2014.
18. B. Raghunathan, Y. Turakhia, S. Garg, and D. Marculescu. Cherry-picking: Exploiting process variations in dark-silicon homogeneous chip multi-processors. In DATE, pages 39-44, 2013.
19. E. Rotem, A. Naveh, D. Rajwan, A. Ananthakrishnan, and E. Weissmann. Power-management architecture of the intel microarchitecture code-named sandy bridge. Micro, IEEE, 32(2):20-27, March 2012.
20. M. Shafique, S. Garg, J. Henkel, and D. Marculescu. The EDA challenges in the dark silicon era: Temperature, reliability, and variability perspectives. In DAC, pages 185:1-185:6, 2014.