Performance enhancement under power constraints using heterogeneous CMOS-TFET multicores

CODES+ISSS'12 - Proceedings of the 10th ACM International Conference on Hardware/Software-Codesign and System Synthesis, Co-located with ESWEEK

Volumn , Issue , 2012, Pages 245-254

  Kultursay, Emre ^a   Swaminathan, Karthik ^a   Saripalli, Vinay ^a   Narayanan, Vijaykrishnan ^a   Kandemir, Mahmut T ^a   Datta, Suman ^a  

^a PENNSYLVANIA STATE UNIVERSITY   (United States)

Author keywords

Heterogeneous multicores; Power aware systems; Power partitioning; TFETs

Indexed keywords

APPLICATION PROGRAMMERS; CORE MODEL; DEVICE MODELS; DEVICE TECHNOLOGIES; DYNAMIC POWER; ENERGY EFFICIENT; HETEROGENEOUS MULTICORE; HETEROGENEOUS PROCESSORS; HIGH ENERGY EFFICIENCY; MULTI CORE; MULTI-CORES; OPERATING POINTS; PERFORMANCE ENHANCEMENTS; POWER AWARE SYSTEM; POWER BUDGETS; POWER CONSTRAINTS; POWER PARTITIONING; RUN-TIME CONFIGURATION; RUNTIMES; TFETS;

HARDWARE;

ENERGY EFFICIENCY;

EID: 84869073803     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1145/2380445.2380487     Document Type: Conference Paper

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