Power-management architecture of the intel microarchitecture code-named Sandy Bridge

IEEE Micro

Volumn 32, Issue 2, 2012, Pages 20-27

  Rotem, Efraim ^a   Naveh, Alon ^a,b   Ananthakrishnan, Avinash ^c   Weissmann, Eliezer ^d   Rajwan, Doron ^a  

^a INTEL CORPORATION   (Israel)

^b SAN JOSE STATE UNIVERSITY   (United States)

^c TEL AVIV UNIVERSITY   (Israel)

^d UNIVERSITY OF MICHIGAN   (United States)

Author keywords

energy management; power management; Sandy Bridge; Turbo Boost

Indexed keywords

ARCHITECTURAL APPROACH; FORM FACTORS; HIGH INTEGRATION LEVEL; MARKET NEEDS; MICRO ARCHITECTURES; MODERN MICROPROCESSOR; PHYSICAL CONSTRAINTS; POWER MANAGEMENTS; SYSTEM-ON-A-CHIP DESIGNS; TURBO BOOST;

APPLICATION SPECIFIC INTEGRATED CIRCUITS; APPROXIMATION THEORY; ENERGY MANAGEMENT; PROGRAM PROCESSORS;

MICROPROCESSOR CHIPS;

EID: 84859729360     PISSN: 02721732     EISSN: None     Source Type: Journal    
DOI: 10.1109/MM.2012.12     Document Type: Article

References (9)

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9. Intersil, Power Management Products- Processor Power, 2012; http://www.intersil. com/processor-power