ASER: Adaptive soft error resilience for reliability-heterogeneous processors in the dark silicon era

Proceedings - Design Automation Conference

Volumn , Issue , 2014, Pages

  Kriebel, Florian ^a   Rehman, Semeen ^a   Sun, Duo ^a   Shafique, Muhammad ^a   Henkel, Jörg ^a  

^a KARLSRUHE INSTITUTE OF TECHNOLOGY   (Germany)

Author keywords

[No Author keywords available]

Indexed keywords

BUDGET CONTROL; COMPUTER AIDED DESIGN; ERROR CORRECTION; RADIATION HARDENING; RELIABILITY; SILICON;

45NM TECHNOLOGY; EMBEDDED PROCESSORS; HETEROGENEOUS PROCESSORS; LEVELS OF PROTECTIONS; RUNTIME SYSTEMS; STATE-OF-THE-ART APPROACH; SYSTEM RELIABILITY; THERMAL DESIGNS;

MICROPROCESSOR CHIPS;

EID: 84903208378     PISSN: 0738100X     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1145/2593069.2593094     Document Type: Conference Paper

References (25)

1. J. Henkel, L. Bauer, N. Dutt, P. Gupta, S. Nassif, M. Shafique, M. Tahoori, N. Wehn, "Reliable On-Chip Systems in the Nano-Era: Lessons Learnt and Future Trends," IEEE Design Automation Conference (DAC), 2013.
2. Int'l technology roadmap for semiconductors, 2009.
3. J. Henkel, L. Bauer, H. Zhang, S. Rehman, M. Shafique, "Multi-Layer Dependability: From Microarchitecture to Application Level", IEEE DAC, 2014.
4. M. Shafique, S. Garg, D. Marculescu, J. Henkel, "The EDA Challenges in the Dark Silicon Era: Temperature, Reliability, and Variability Perspectives", DAC, 2014.
5. J. Hu, S. Wang, S. G. Ziavras, "In-Register Duplication: Exploiting Narrow-Width Value for Improving Register File Reliability," DSN, pp. 281-290, 2006.
6. S. Rehman, M. Shafique, F. Kriebel, J. Henkel, "Reliable software for unreliable hardware: Embedded code generation aiming at reliability", Codess+ISSS, pp. 237-246, 2011.
7. S. Rehman, A. Toma, F. Kriebel, M. Shafique, J.-J. Chen, J. Henkel, "Reliable Code Generation and Execution on Unreliable Hardware under Joint Functional and Timing Reliability Considerations," IEEE RTAS, pp. 273-282, 2013.
8. R. Vadlamani, J. Zhao, W. Burleson, R. Tessier,"Multicore soft error rate stabilization using adaptive dual modular redundancy", DATE, pp. 27-32, 2010.
9. M. Portolan, R. Leveugle, "A Highly Flexible Hardened RTL Processor Core Based on LEON," European Conference on Radiation and Its Effects on Components and Systems, pp.J7-1,J7-6, 2005.
10. A.Shye, T. Moseley, V. Janapa Reddi, J. Blomstedt, D. A. Connors, "Using Process-Level Redundancy to Exploit Multiple Cores for Transient Fault Tolerance," DSN, pp. 297-306, 2007.
11. C. Bolchini, M. Carminati, A. Miele, "Self-Adaptive Fault Tolerance in Multi-/Many-Core Systems," IEEE Journal of ET, vol. 29, pp. 159-175, 2013.
12. S K. Reinhardt, S. S. Mukherjee, "Transient Fault Detection via Simultaneous Multithreading," ISCA, pp. 25-34, 2000.
13. S. S. Mukherjee, M. Kontz, S. K. Reinhardt, "Detailed design and evaluation of redundant multithreading alternatives," IEEE ISCA, pp. 99-110, 2002.
14. M. Shafique, S. Rehman, P. V. Aceituno, J. Henkel, "Exploiting Program-Level Masking and Error Propagation for Constrained Reliability Optimization," IEEE DAC, pp. 2013.
15. H. Esmaeilzadeh, E. Blem, R. St. Amant, K. Sankaralingam, D. Burger, "Dark silicon and the end of multicore scaling", IEEE ISCA, pp. 365-376, 2011.
16. Michael B Taylor. Is dark silicon useful?: harnessing the four horsemen of the coming dark silicon apocalypse. In Proceedings of the 49th Annual Design Automation Conference, pages 1131-1136. ACM, 2012.
17. J. Cong, M. A. Ghodrat, M. Gill, B. Grigorian, G. Reinman, "Architecture support for accelerator-rich CMPs", IEEE DAC, pp. 843-849, 2012.
18. K. Swaminathan, E. Kultursay, V. Saripalli, V. Narayanan, M. T. Kandemir, S. Datta, "Steep-slope devices: From dark to dim silicon", IEEE Micro, 33(5):50-59, Sept 2013.
19. S. T. Muthukaruppan, M. Pricopi, V. Venkataramani, T. Mitra, S. Vishin, "Hierarchical power management for asymmetric multi-core in dark silicon era", IEEE DAC, 2013.
20. G. Venkatesh et al., "Conservation cores: reducing the energy of mature computations", ASPLOS, pp. 205-218, 2010.
21. Y. Turakhia, B. Raghunathan, S. Garg, D. Marculescu, "Hades: Architectural synthesis for heterogeneous dark silicon chip multi- processors", IEEE DAC, 2013.
22. T. Li, M. Shafique, S. Rehman, J. A. Ambrose, J. Henkel, S. Parameswaran, "DHASER: Dynamic Heterogeneous Adaptation for Soft-Error Resiliency in ASIP-based Multi-core Systems," IEEE ICCAD, 2013.
23. B. Raghunathan, Y. Turakhia, S. Garg, D. Marculescu, "Cherry- Picking: Exploiting Process Variations in Dark-Silicon Homogeneous Chip Multi-Processors", IEEE DATE, pp. 39-44, 2013.
24. Flux calculator: www.seutest.com/cgi-bin/FluxCalculator.cgi.
25. A. Singh, M. Shafique, A. Kumar, J. Henkel, "Mapping on multi/manycore systems: Survey of current and emerging trends", IEEE DAC, 2013.