Cherry-picking: Exploiting process variations in dark-silicon homogeneous chip multi-processors

Proceedings -Design, Automation and Test in Europe, DATE

Volumn , Issue , 2013, Pages 39-44

  Raghunathan, Bharathwaj ^a   Turakhia, Yatish ^b   Garg, Siddharth ^a   Marculescu, Diana ^c  

^a UNIVERSITY OF WATERLOO   (Canada)

^b INDIAN INSTITUTE OF TECHNOLOGY BOMBAY   (India)

^c CARNEGIE MELLON UNIVERSITY   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

BUDGET CONTROL; POLYNOMIAL APPROXIMATION;

CHIP MULTI-PROCESSORS; FREQUENCY ASSIGNMENTS; HETEROGENEOUS RESOURCES; IN-PROCESS PARAMETERS; MULTI- THREADED APPLICATIONS; ON-CHIP INTEGRATION; POLYNOMIAL-TIME ALGORITHMS; SCALED TECHNOLOGIES;

SILICON;

EID: 84885641092     PISSN: 15301591     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.7873/date.2013.023     Document Type: Conference Paper

References (16)

1. Christian Bienia, Sanjeev Kumar, Jaswinder Pal Singh, and Kai Li. The parsec benchmark suite: characterization and architectural implications. In Proceedings of the 17th international conference on Parallel architectures and compilation techniques, PACT '08, pages 72-81, 2008.
2. K.A. Bowman, S.G. Duvall, and J.D. Meindl. Impact of die-to-die and within-die parameter fluctuations on the maximum clock frequency distribution for gigascale integration. Solid-State Circuits, IEEE Journal of, 37(2): 183-190, 2002.
3. T.E. Carlson, W. Heirman, and L. Eeckhout. Sniper: Exploring the level of abstraction for scalable and accurate parallel multi-core simulation. In High Performance Computing, Networking, Storage and Analysis (SC), 2011 International Conference for, pages 1-12, 2011.
4. S. Dighe, S.R. Vangal, P. Aseron, S. Kumar, T. Jacob, K.A. Bowman, J. Howard, J. Tschanz, V. Erraguntla, N. Borkar, V.K. De, and S. Borkar. Within-die variation-aware dynamic-voltage-frequency-scaling with optimal core allocation and thread hopping for the 80-core teraflops processor. Solid-State Circuits, IEEE Journal of, 46(1): 184-193, 2011.
5. H. Esmaeilzadeh, E. Blem, R.S. Amant, K. Sankaralingam, and D. Burger. Dark silicon and the end of multicore scaling. In Computer Architecture (ISCA), 2011 38th Annual International Symposium on, pages 365-376, 2011.
6. N. Goulding-Hotta, J. Sampson, G. Venkatesh, S. Garcia, J. Auricchio, P. Huang, M. Arora, S. Nath, V. Bhatt, J. Babb, S. Swanson, and M. Taylor. The greendroid mobile application processor: An architecture for silicon's dark future. Volume 31, pages 86-95, 2011.
7. S. Herbert, S. Garg, and D. Marculescu. Exploiting process variability in voltage/frequency control. Very Large Scale Integration (VLSI) Systems, IEEE Transactions on, 20(8): 1392-1404, 2012.
8. S. Herbert and D. Marculescu. Characterizing chip-multiprocessor variability-tolerance. In Design Automation Conference, 2008. DAC 2008. 45th ACM/IEEE, pages 313-318, 2008.
9. U.R. Karpuzcu, B. Greskamp, and J. Torrellas. The bubblewrap many-core: Popping cores for sequential acceleration. In Microarchitecture, 2009. MICRO-42. 42nd Annual IEEE/ACM International Symposium on, pages 447-458, 2009.
10. J. Lee and N.S. Kim. Optimizing throughput of power-and thermal-constrained multicore processors using dvfs and per-core power-gating. In Design Automation Conference, 2009. DAC'09. 46th ACM/IEEE, pages 47-50, 2009.
11. Sheng Li, Jung Ho Ahn, R.D. Strong, J.B. Brockman, D.M. Tullsen, and N.P. Jouppi. Mcpat: An integrated power, area, and timing modeling framework for multicore and manycore architectures. In Microarchitecture, 2009. MICRO-42. 42nd Annual IEEE/ACM International Symposium on, pages 469-480, 2009.
12. Daniel Shelepov, Juan Carlos Saez Alcaide, Stacey Jeffery, Alexandra Fedorova, Nestor Perez, Zhi Feng Huang, Sergey Blagodurov, and Viren Kumar. Hass: a scheduler for heterogeneous multicore systems. SIGOPS Oper. Syst. Rev., 43(2): 66-75, 2009.
13. Radu Teodorescu and Josep Torrellas. Variation-aware application scheduling and power management for chip multiprocessors. SIGARCH Comput. Archit. News, 36(3): 363-374, 2008.
14. J.A. Winter and D.H. Albonesi. Scheduling algorithms for unpredictably heterogeneous cmp architectures. In Dependable Systems and Networks With FTCS and DCC, 2008. DSN 2008. IEEE International Conference on, pages 42-51, 2008.
15. Steven Cameron Woo, Moriyoshi Ohara, Evan Torrie, Jaswinder Pal Singh, and Anoop Gupta. The splash-2 programs: characterization and methodological considerations. In Proceedings of the 22nd annual international symposium on Computer architecture, ISCA '95, pages 24-36, 1995.
16. Jinjun Xiong, V. Zolotov, and Lei He. Robust extraction of spatial correlation. Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on, 26(4): 619-631, 2007.