QNoC asynchronous router with dynamic virtual channel allocation

Proceedings - NOCS 2007: First International Symposium on Networks-on-Chip

Volumn , Issue , 2007, Pages 218-

  Dobkin, Rostislav ^a   Ginosar, Ran ^a   Cidon, Israel ^a  

^a TECHNION ISRAEL INSTITUTE OF TECHNOLOGY   (Israel)

Author keywords

[No Author keywords available]

Indexed keywords

MICROPROCESSOR CHIPS; OPTIMIZATION; QUALITY OF SERVICE; VIRTUAL REALITY;

CHANNEL ALLOCATION; FAST ARBITRATION; LATENCY; VIRTUAL CHANNELS (VC);

ROUTERS;

EID: 36349035125     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/NOCS.2007.36     Document Type: Conference Paper

References (5)

1. ITRS. 2005. www.itrs.net.
2. W.J. Dally et al., "Route Packets, Not Wires: On-Chip Interconnection Networks," Proc. DAC, pp.684-689, 2001.
3. E. Bolotin et al, "QoS Architecture and Design Process for Cost Effective Networks on Chip", J. Systems Architecture, special issue on NoC, 50(2-3):105-128, 2004.
4. R. Dobkin et al., "An Asynchronous Router for Multiple Service Levels Networks on Chip," Proc. ASYNC'05:44-53.
5. R. Dobkin et al., "QNoC Asynchronous Router with Dynamic Virtual Channel Allocation," http://www.ee.technion.ac.il/~ran/papers/ARtrVC.pdf.